c912ac66b3
This is a platform/x86 library that is mostly being used by other drivers not directly under arch/x86 anyway (with the exception of the Intel MID setup code) so it makes sense that it lives under the platform_data/x86/ directory instead. No functional changes intended. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240909124952.1152017-3-andriy.shevchenko@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
153 lines
3.4 KiB
C
153 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Intel SCU IPC mechanism
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*
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* (C) Copyright 2008-2010 Intel Corporation
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* Author: Sreedhara DS (sreedhara.ds@intel.com)
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*
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* This driver provides IOCTL interfaces to call Intel SCU IPC driver API.
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*/
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#include <linux/errno.h>
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#include <linux/fcntl.h>
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#include <linux/fs.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/platform_data/x86/intel_scu_ipc.h>
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static int major;
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static struct intel_scu_ipc_dev *scu;
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static DEFINE_MUTEX(scu_lock);
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/* IOCTL commands */
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#define INTE_SCU_IPC_REGISTER_READ 0
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#define INTE_SCU_IPC_REGISTER_WRITE 1
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#define INTE_SCU_IPC_REGISTER_UPDATE 2
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struct scu_ipc_data {
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u32 count; /* No. of registers */
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u16 addr[5]; /* Register addresses */
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u8 data[5]; /* Register data */
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u8 mask; /* Valid for read-modify-write */
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};
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/**
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* scu_reg_access - implement register access ioctls
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* @cmd: command we are doing (read/write/update)
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* @data: kernel copy of ioctl data
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*
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* Allow the user to perform register accesses on the SCU via the
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* kernel interface
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*/
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static int scu_reg_access(u32 cmd, struct scu_ipc_data *data)
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{
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unsigned int count = data->count;
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if (count == 0 || count == 3 || count > 4)
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return -EINVAL;
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switch (cmd) {
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case INTE_SCU_IPC_REGISTER_READ:
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return intel_scu_ipc_dev_readv(scu, data->addr, data->data, count);
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case INTE_SCU_IPC_REGISTER_WRITE:
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return intel_scu_ipc_dev_writev(scu, data->addr, data->data, count);
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case INTE_SCU_IPC_REGISTER_UPDATE:
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return intel_scu_ipc_dev_update(scu, data->addr[0], data->data[0],
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data->mask);
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default:
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return -ENOTTY;
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}
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}
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/**
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* scu_ipc_ioctl - control ioctls for the SCU
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* @fp: file handle of the SCU device
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* @cmd: ioctl coce
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* @arg: pointer to user passed structure
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*
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* Support the I/O and firmware flashing interfaces of the SCU
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*/
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static long scu_ipc_ioctl(struct file *fp, unsigned int cmd,
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unsigned long arg)
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{
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int ret;
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struct scu_ipc_data data;
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void __user *argp = (void __user *)arg;
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if (!capable(CAP_SYS_RAWIO))
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return -EPERM;
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if (copy_from_user(&data, argp, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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ret = scu_reg_access(cmd, &data);
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if (ret < 0)
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return ret;
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if (copy_to_user(argp, &data, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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return 0;
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}
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static int scu_ipc_open(struct inode *inode, struct file *file)
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{
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int ret = 0;
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/* Only single open at the time */
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mutex_lock(&scu_lock);
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if (scu) {
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ret = -EBUSY;
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goto unlock;
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}
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scu = intel_scu_ipc_dev_get();
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if (!scu)
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ret = -ENODEV;
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unlock:
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mutex_unlock(&scu_lock);
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return ret;
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}
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static int scu_ipc_release(struct inode *inode, struct file *file)
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{
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mutex_lock(&scu_lock);
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intel_scu_ipc_dev_put(scu);
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scu = NULL;
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mutex_unlock(&scu_lock);
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return 0;
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}
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static const struct file_operations scu_ipc_fops = {
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.unlocked_ioctl = scu_ipc_ioctl,
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.open = scu_ipc_open,
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.release = scu_ipc_release,
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};
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static int __init ipc_module_init(void)
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{
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major = register_chrdev(0, "intel_mid_scu", &scu_ipc_fops);
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if (major < 0)
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return major;
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return 0;
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}
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static void __exit ipc_module_exit(void)
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{
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unregister_chrdev(major, "intel_mid_scu");
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}
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module_init(ipc_module_init);
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module_exit(ipc_module_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Utility driver for intel scu ipc");
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MODULE_AUTHOR("Sreedhara <sreedhara.ds@intel.com>");
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