947bb8f24b
The flash ID is the new primary key into our database. Sort the entry by it. Keep the most specific ones first, because there might be ID collisions between shorter and longer ones. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20230807-mtd-flash-info-db-rework-v3-34-e60548861b10@kernel.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
147 lines
3.6 KiB
C
147 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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is25lp256_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* IS25LP256 supports 4B opcodes, but the BFPT advertises
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* BFPT_DWORD1_ADDRESS_BYTES_3_ONLY.
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* Overwrite the number of address bytes advertised by the BFPT.
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*/
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if ((bfpt->dwords[SFDP_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
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BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
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nor->params->addr_nbytes = 4;
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return 0;
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}
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static const struct spi_nor_fixups is25lp256_fixups = {
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.post_bfpt = is25lp256_post_bfpt_fixups,
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};
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static int pm25lv_nor_late_init(struct spi_nor *nor)
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{
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struct spi_nor_erase_map *map = &nor->params->erase_map;
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int i;
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/* The PM25LV series has a different 4k sector erase opcode */
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for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++)
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if (map->erase_type[i].size == 4096)
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map->erase_type[i].opcode = SPINOR_OP_BE_4K_PMC;
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return 0;
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}
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static const struct spi_nor_fixups pm25lv_nor_fixups = {
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.late_init = pm25lv_nor_late_init,
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};
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static const struct flash_info issi_nor_parts[] = {
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{
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.name = "pm25lv512",
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.sector_size = SZ_32K,
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.size = SZ_64K,
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.no_sfdp_flags = SECT_4K,
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.fixups = &pm25lv_nor_fixups
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}, {
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.name = "pm25lv010",
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.sector_size = SZ_32K,
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.size = SZ_128K,
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.no_sfdp_flags = SECT_4K,
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.fixups = &pm25lv_nor_fixups
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}, {
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.id = SNOR_ID(0x7f, 0x9d, 0x20),
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.name = "is25cd512",
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.sector_size = SZ_32K,
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.size = SZ_64K,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0x7f, 0x9d, 0x46),
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.name = "pm25lq032",
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.size = SZ_4M,
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.no_sfdp_flags = SECT_4K,
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}, {
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.id = SNOR_ID(0x9d, 0x40, 0x13),
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.name = "is25lq040b",
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.size = SZ_512K,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x14),
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.name = "is25lp080d",
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.size = SZ_1M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x15),
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.name = "is25lp016d",
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.size = SZ_2M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x16),
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.name = "is25lp032",
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.size = SZ_4M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x17),
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.name = "is25lp064",
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.size = SZ_8M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x18),
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.name = "is25lp128",
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.size = SZ_16M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x60, 0x19),
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.name = "is25lp256",
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.fixups = &is25lp256_fixups,
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.fixup_flags = SPI_NOR_4B_OPCODES,
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}, {
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.id = SNOR_ID(0x9d, 0x70, 0x16),
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.name = "is25wp032",
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.size = SZ_4M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x70, 0x17),
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.size = SZ_8M,
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.name = "is25wp064",
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x70, 0x18),
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.name = "is25wp128",
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.size = SZ_16M,
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.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
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}, {
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.id = SNOR_ID(0x9d, 0x70, 0x19),
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.name = "is25wp256",
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.flags = SPI_NOR_QUAD_PP,
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.fixups = &is25lp256_fixups,
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.fixup_flags = SPI_NOR_4B_OPCODES,
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}
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};
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static void issi_nor_default_init(struct spi_nor *nor)
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{
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static const struct spi_nor_fixups issi_fixups = {
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.default_init = issi_nor_default_init,
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};
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const struct spi_nor_manufacturer spi_nor_issi = {
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.name = "issi",
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.parts = issi_nor_parts,
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.nparts = ARRAY_SIZE(issi_nor_parts),
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.fixups = &issi_fixups,
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};
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