d6bbc4da21
Some plane B/C specific bits were left next to the unused _DSPBCNTR macro. Move them next to the DSPCNTR() macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/85409fbe5073797c0dc17df43eeb25abe9ff889f.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
113 lines
5.1 KiB
C
113 lines
5.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef __I9XX_PLANE_REGS_H__
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#define __I9XX_PLANE_REGS_H__
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#include "intel_display_reg_defs.h"
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#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
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#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
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#define _DSPACNTR 0x70180
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#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
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#define DISP_ENABLE REG_BIT(31)
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#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
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#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
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#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
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#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
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#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
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#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
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#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
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#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
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#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
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#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
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#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
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#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
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#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
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#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
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#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
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#define DISP_STEREO_ENABLE REG_BIT(25)
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#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
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#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
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#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
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#define DISP_SRC_KEY_ENABLE REG_BIT(22)
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#define DISP_LINE_DOUBLE REG_BIT(20)
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#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
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#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
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#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
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#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
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#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
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#define DISP_TILED REG_BIT(10) /* i965+ */
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#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
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#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
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#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */
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#define _DSPAADDR 0x70184 /* pre-i965 */
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#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
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#define _DSPALINOFF 0x70184 /* i965+ */
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#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
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#define _DSPASTRIDE 0x70188
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#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
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#define _DSPAPOS 0x7018C /* pre-g4x */
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#define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
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#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
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#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
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#define DISP_POS_X_MASK REG_GENMASK(15, 0)
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#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
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#define _DSPASIZE 0x70190 /* pre-g4x */
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#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
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#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
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#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
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#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
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#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
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#define _DSPASURF 0x7019C /* i965+ */
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#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
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#define DISP_ADDR_MASK REG_GENMASK(31, 12)
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#define _DSPATILEOFF 0x701A4 /* i965+ */
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#define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
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#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
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#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
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#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
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#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
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#define _DSPAOFFSET 0x701A4 /* hsw+ */
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#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
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#define _DSPASURFLIVE 0x701AC /* g4x+ */
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#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
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#define _DSPAGAMC 0x701E0 /* pre-g4x */
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#define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
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/* CHV pipe B primary plane */
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#define _PRIMPOS_A 0x60a08
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#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
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#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
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#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
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#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
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#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
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#define _PRIMSIZE_A 0x60a0c
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#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
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#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
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#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
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#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
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#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
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#define _PRIMCNSTALPHA_A 0x60a10
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#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
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#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
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#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
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#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
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#endif /* __I9XX_PLANE_REGS_H__ */
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