ada8f95ba0
Add support for mapping reset IDs to register offsets to support gapless continous platform reset IDs. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
127 lines
3.0 KiB
C
127 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include "clk.h"
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struct rockchip_softrst {
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struct reset_controller_dev rcdev;
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const int *lut;
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void __iomem *reg_base;
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int num_regs;
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int num_per_reg;
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u8 flags;
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spinlock_t lock;
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};
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static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_softrst *softrst = container_of(rcdev,
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struct rockchip_softrst,
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rcdev);
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int bank, offset;
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if (softrst->lut)
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id = softrst->lut[id];
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bank = id / softrst->num_per_reg;
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offset = id % softrst->num_per_reg;
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if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
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writel(BIT(offset) | (BIT(offset) << 16),
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softrst->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&softrst->lock, flags);
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reg = readl(softrst->reg_base + (bank * 4));
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writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
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spin_unlock_irqrestore(&softrst->lock, flags);
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}
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return 0;
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}
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static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_softrst *softrst = container_of(rcdev,
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struct rockchip_softrst,
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rcdev);
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int bank, offset;
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if (softrst->lut)
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id = softrst->lut[id];
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bank = id / softrst->num_per_reg;
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offset = id % softrst->num_per_reg;
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if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
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writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&softrst->lock, flags);
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reg = readl(softrst->reg_base + (bank * 4));
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writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
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spin_unlock_irqrestore(&softrst->lock, flags);
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}
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return 0;
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}
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static const struct reset_control_ops rockchip_softrst_ops = {
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.assert = rockchip_softrst_assert,
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.deassert = rockchip_softrst_deassert,
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};
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void rockchip_register_softrst_lut(struct device_node *np,
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const int *lookup_table,
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unsigned int num_regs,
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void __iomem *base, u8 flags)
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{
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struct rockchip_softrst *softrst;
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int ret;
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softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
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if (!softrst)
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return;
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spin_lock_init(&softrst->lock);
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softrst->reg_base = base;
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softrst->lut = lookup_table;
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softrst->flags = flags;
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softrst->num_regs = num_regs;
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softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
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: 32;
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softrst->rcdev.owner = THIS_MODULE;
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if (lookup_table)
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softrst->rcdev.nr_resets = num_regs;
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else
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softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
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softrst->rcdev.ops = &rockchip_softrst_ops;
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softrst->rcdev.of_node = np;
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ret = reset_controller_register(&softrst->rcdev);
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if (ret) {
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pr_err("%s: could not register reset controller, %d\n",
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__func__, ret);
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kfree(softrst);
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}
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};
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EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut);
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