1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines for the Atlas interrupt controller.
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*
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*/
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#ifndef _MIPS_ATLASINT_H
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#define _MIPS_ATLASINT_H
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#define ATLASINT_BASE 1
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#define ATLASINT_UART (ATLASINT_BASE+0)
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#define ATLASINT_TIM0 (ATLASINT_BASE+1)
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#define ATLASINT_RES2 (ATLASINT_BASE+2)
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#define ATLASINT_RES3 (ATLASINT_BASE+3)
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#define ATLASINT_RTC (ATLASINT_BASE+4)
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#define ATLASINT_COREHI (ATLASINT_BASE+5)
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#define ATLASINT_CORELO (ATLASINT_BASE+6)
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#define ATLASINT_RES7 (ATLASINT_BASE+7)
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#define ATLASINT_PCIA (ATLASINT_BASE+8)
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#define ATLASINT_PCIB (ATLASINT_BASE+9)
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#define ATLASINT_PCIC (ATLASINT_BASE+10)
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#define ATLASINT_PCID (ATLASINT_BASE+11)
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#define ATLASINT_ENUM (ATLASINT_BASE+12)
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#define ATLASINT_DEG (ATLASINT_BASE+13)
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#define ATLASINT_ATXFAIL (ATLASINT_BASE+14)
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#define ATLASINT_INTA (ATLASINT_BASE+15)
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#define ATLASINT_INTB (ATLASINT_BASE+16)
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#define ATLASINT_ETH ATLASINT_INTB
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#define ATLASINT_INTC (ATLASINT_BASE+17)
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#define ATLASINT_SCSI ATLASINT_INTC
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#define ATLASINT_INTD (ATLASINT_BASE+18)
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#define ATLASINT_SERR (ATLASINT_BASE+19)
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#define ATLASINT_RES20 (ATLASINT_BASE+20)
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#define ATLASINT_RES21 (ATLASINT_BASE+21)
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#define ATLASINT_RES22 (ATLASINT_BASE+22)
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#define ATLASINT_RES23 (ATLASINT_BASE+23)
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#define ATLASINT_RES24 (ATLASINT_BASE+24)
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#define ATLASINT_RES25 (ATLASINT_BASE+25)
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#define ATLASINT_RES26 (ATLASINT_BASE+26)
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#define ATLASINT_RES27 (ATLASINT_BASE+27)
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#define ATLASINT_RES28 (ATLASINT_BASE+28)
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#define ATLASINT_RES29 (ATLASINT_BASE+29)
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#define ATLASINT_RES30 (ATLASINT_BASE+30)
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#define ATLASINT_RES31 (ATLASINT_BASE+31)
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#define ATLASINT_END (ATLASINT_BASE+31)
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/*
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* Atlas registers are memory mapped on 64-bit aligned boundaries and
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* only word access are allowed.
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*/
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struct atlas_ictrl_regs {
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volatile unsigned int intraw;
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int dummy1;
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volatile unsigned int intseten;
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int dummy2;
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volatile unsigned int intrsten;
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int dummy3;
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volatile unsigned int intenable;
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int dummy4;
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volatile unsigned int intstatus;
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int dummy5;
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};
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extern void atlasint_init(void);
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#endif /* !(_MIPS_ATLASINT_H) */
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