49148020bc
Merge header files for m68k and m68knommu to the single location:
arch/m68k/include/asm
The majority of this patch was the result of the
script that is included in the changelog below.
The script was originally written by Arnd Bergman and
exten by me to cover a few more files.
When the header files differed the script uses the following:
The original m68k file is named <file>_mm.h [mm for memory manager]
The m68knommu file is named <file>_no.h [no for no memory manager]
The files uses the following include guard:
This include gaurd works as the m68knommu toolchain set
the __uClinux__ symbol - so this should work in userspace too.
Merging the header files for m68k and m68knommu exposes the
(unexpected?) ABI differences thus it is easier to actually
identify these and thus to fix them.
The commit has been build tested with both a m68k and
a m68knommu toolchain - with success.
The commit has also been tested with "make headers_check"
and this patch fixes make headers_check for m68knommu.
The script used:
TARGET=arch/m68k/include/asm
SOURCE=arch/m68knommu/include/asm
INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \
linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \
oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \
shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \
termbits.h termios.h tlb.h types.h user.h"
EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \
ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \
sections.h topology.h"
NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \
elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \
m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \
m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \
m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \
mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \
mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \
nettel.h quicc_simple.h smp.h"
FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \
cacheflush.h checksum.h current.h delay.h div64.h \
dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \
irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \
module.h page.h page_offset.h param.h pci.h pgalloc.h \
pgtable.h processor.h ptrace.h scatterlist.h segment.h \
setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \
thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \
unaligned.h unistd.h"
mergefile() {
BASE=${1%.h}
git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h
git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h
cat << EOF > ${TARGET}/$1
EOF
git add ${TARGET}/$1
}
set -e
mkdir -p ${TARGET}
git mv include/asm-m68k/* ${TARGET}
rmdir include/asm-m68k
git rm ${SOURCE}/Kbuild
for F in $INCLUDE $EQUAL; do
git rm ${SOURCE}/$F
done
for F in $NOMUUFILES; do
git mv ${SOURCE}/$F ${TARGET}/$F
done
for F in $FILES ; do
mergefile $F
done
rmdir arch/m68knommu/include/asm
rmdir arch/m68knommu/include
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
79 lines
3.3 KiB
C
79 lines
3.3 KiB
C
/****************************************************************************/
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/*
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* m5272sim.h -- ColdFire 5272 System Integration Module support.
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*
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef m5272sim_h
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#define m5272sim_h
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/****************************************************************************/
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/*
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* Define the 5272 SIM register set addresses.
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*/
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#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
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#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
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#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
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#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
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#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
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#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
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#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
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#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
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#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
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#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
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#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
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#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
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#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
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#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
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#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
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#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
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#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
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#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
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#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
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#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
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#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
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#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
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#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
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#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
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#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
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#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
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#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
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#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
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#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
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#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
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#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
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#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */
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#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */
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#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */
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#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */
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#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */
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#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */
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#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */
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#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */
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#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */
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/****************************************************************************/
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#endif /* m5272sim_h */
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