190de00538
This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* Copyright 2007 David Gibson, IBM Corporation.
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*
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* Based on earlier code:
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* Copyright (C) Paul Mackerras 1997.
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "string.h"
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#include "stdio.h"
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#include "page.h"
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#include "ops.h"
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#include "reg.h"
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#include "io.h"
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#include "dcr.h"
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#include "4xx.h"
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#include "44x.h"
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static u8 *ebony_mac0, *ebony_mac1;
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#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
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#define EBONY_FPGA_FLASH_SEL 0x01
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#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
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static void ebony_flashsel_fixup(void)
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{
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void *devp;
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u32 reg[3] = {0x0, 0x0, 0x80000};
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u8 *fpga;
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u8 fpga_reg0 = 0x0;
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devp = finddevice(EBONY_FPGA_PATH);
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if (!devp)
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fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH);
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if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
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fatal("%s has missing or invalid virtual-reg property\n\r",
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EBONY_FPGA_PATH);
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fpga_reg0 = in_8(fpga);
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devp = finddevice(EBONY_SMALL_FLASH_PATH);
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if (!devp)
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fatal("Couldn't locate small flash node %s\n\r",
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EBONY_SMALL_FLASH_PATH);
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if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg))
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fatal("%s has reg property of unexpected size\n\r",
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EBONY_SMALL_FLASH_PATH);
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/* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */
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if (fpga_reg0 & EBONY_FPGA_FLASH_SEL)
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reg[1] ^= 0x80000;
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setprop(devp, "reg", reg, sizeof(reg));
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}
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static void ebony_fixups(void)
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{
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// FIXME: sysclk should be derived by reading the FPGA registers
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unsigned long sysclk = 33000000;
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ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
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ibm4xx_sdram_fixup_memsize();
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dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
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ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
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ebony_flashsel_fixup();
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}
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void ebony_init(void *mac0, void *mac1)
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{
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platform_ops.fixups = ebony_fixups;
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platform_ops.exit = ibm44x_dbcr_reset;
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ebony_mac0 = mac0;
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ebony_mac1 = mac1;
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fdt_init(_dtb_start);
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serial_console_init();
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}
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