8785a8fbd5
PXA3 has a different memory controller from PXA2 platforms. Avoid clashing definitions by moving the PXA2 definitions to pxa2xx-regs.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
85 lines
4.1 KiB
C
85 lines
4.1 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/pxa2xx-regs.h
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*
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* Taken from pxa-regs.h by Russell King
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*
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* Author: Nicolas Pitre
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PXA2XX_REGS_H
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#define __PXA2XX_REGS_H
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/*
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* Memory controller
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*/
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#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
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#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
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#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
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#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
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#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
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#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
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#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
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#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
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#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
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#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
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#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
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#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
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#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
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#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
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#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
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#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
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#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
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/*
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* More handy macros for PCMCIA
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*
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* Arg is socket number
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*/
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#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
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#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
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#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
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/* MECR register defines */
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#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
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#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
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#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
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#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
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#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
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#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
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#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
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#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
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#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
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#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
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#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
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#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
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#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
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#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
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#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
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#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
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#ifdef CONFIG_PXA27x
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#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
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#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
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#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
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#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
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#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
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#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
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#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
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#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
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#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
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#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
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#endif
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#endif
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