557 lines
25 KiB
C
557 lines
25 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/pxa-regs.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PXA_REGS_H
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#define __PXA_REGS_H
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/*
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* PXA Chip selects
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*/
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#define PXA_CS0_PHYS 0x00000000
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#define PXA_CS1_PHYS 0x04000000
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#define PXA_CS2_PHYS 0x08000000
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#define PXA_CS3_PHYS 0x0C000000
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#define PXA_CS4_PHYS 0x10000000
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#define PXA_CS5_PHYS 0x14000000
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/*
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* Personal Computer Memory Card International Association (PCMCIA) sockets
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*/
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#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
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#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
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#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
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#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
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#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
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#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
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#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
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#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
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#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
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#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
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#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
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#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
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#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
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#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
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(0x20000000 + (Nb)*PCMCIASp)
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#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
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#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
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(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
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#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
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(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
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#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
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#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
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#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
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#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
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#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
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#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
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#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
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#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
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/*
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* DMA Controller
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*/
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#define DCSR(x) __REG2(0x40000000, (x) << 2)
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#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
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#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
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#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
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#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
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#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
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#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
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#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
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#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
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#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
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#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
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#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
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#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
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#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR (1 << 9) /* The end of Receive */
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#endif
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#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
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#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
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#define DRCMR(n) (*(((n) < 64) ? \
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&__REG2(0x40000100, ((n) & 0x3f) << 2) : \
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&__REG2(0x40001100, ((n) & 0x3f) << 2)))
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#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
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#define DDADR(x) __REG2(0x40000200, (x) << 4)
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#define DSADR(x) __REG2(0x40000204, (x) << 4)
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#define DTADR(x) __REG2(0x40000208, (x) << 4)
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#define DCMD(x) __REG2(0x4000020c, (x) << 4)
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#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
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#define DDADR_STOP (1 << 0) /* Stop (read / write) */
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#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
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#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
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#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
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#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
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#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
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#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
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#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
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#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
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#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
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#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
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#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
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#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
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#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
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#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/*
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* UARTs
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*/
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/* Full Function UART (FFUART) */
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#define FFUART FFRBR
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#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
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#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
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#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
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#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
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#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
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#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
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#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
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#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
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#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
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#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
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#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
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#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Bluetooth UART (BTUART) */
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#define BTUART BTRBR
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#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
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#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
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#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
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#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
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#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
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#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
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#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
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#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
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#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
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#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
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#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
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#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Standard UART (STUART) */
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#define STUART STRBR
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#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
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#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
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#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
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#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
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#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
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#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
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#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
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#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
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#define STMSR __REG(0x40700018) /* Reserved */
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#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
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#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
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#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Hardware UART (HWUART) */
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#define HWUART HWRBR
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#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
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#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
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#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
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#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
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#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
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#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
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#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
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#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
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#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
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#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
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#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
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#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
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#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
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#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
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#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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#define IER_DMAE (1 << 7) /* DMA Requests Enable */
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#define IER_UUE (1 << 6) /* UART Unit Enable */
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#define IER_NRZE (1 << 5) /* NRZ coding Enable */
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#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
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#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
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#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
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#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
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#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
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#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
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#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
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#define IIR_TOD (1 << 3) /* Time Out Detected */
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#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
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#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
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#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
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#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
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#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
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#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
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#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
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#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
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#define FCR_ITL_1 (0)
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#define FCR_ITL_8 (FCR_ITL1)
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#define FCR_ITL_16 (FCR_ITL2)
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#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
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#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define LCR_SB (1 << 6) /* Set Break */
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#define LCR_STKYP (1 << 5) /* Sticky Parity */
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#define LCR_EPS (1 << 4) /* Even Parity Select */
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#define LCR_PEN (1 << 3) /* Parity Enable */
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#define LCR_STB (1 << 2) /* Stop Bit */
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#define LCR_WLS1 (1 << 1) /* Word Length Select */
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#define LCR_WLS0 (1 << 0) /* Word Length Select */
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#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
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#define LSR_TEMT (1 << 6) /* Transmitter Empty */
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#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
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#define LSR_BI (1 << 4) /* Break Interrupt */
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#define LSR_FE (1 << 3) /* Framing Error */
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#define LSR_PE (1 << 2) /* Parity Error */
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#define MCR_LOOP (1 << 4)
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#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
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#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
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#define MCR_RTS (1 << 1) /* Request to Send */
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#define MCR_DTR (1 << 0) /* Data Terminal Ready */
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#define MSR_DCD (1 << 7) /* Data Carrier Detect */
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#define MSR_RI (1 << 6) /* Ring Indicator */
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#define MSR_DSR (1 << 5) /* Data Set Ready */
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#define MSR_CTS (1 << 4) /* Clear To Send */
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#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
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#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
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#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
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#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
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/*
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* IrSR (Infrared Selection Register)
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*/
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#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
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#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
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#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
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#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
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#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
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/*
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* I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
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*/
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/*
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* Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
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*/
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/*
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* AC97 Controller registers
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*/
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#define POCR __REG(0x40500000) /* PCM Out Control Register */
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#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define PICR __REG(0x40500004) /* PCM In Control Register */
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#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MCCR __REG(0x40500008) /* Mic In Control Register */
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#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
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#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define GCR __REG(0x4050000C) /* Global Control Register */
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#ifdef CONFIG_PXA3xx
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#define GCR_CLKBPB (1 << 31) /* Internal clock enable */
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#endif
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#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
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#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
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#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
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#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
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#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
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#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
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#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
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#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
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#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
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#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
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#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
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#define POSR __REG(0x40500010) /* PCM Out Status Register */
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#define POSR_FIFOE (1 << 4) /* FIFO error */
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#define POSR_FSR (1 << 2) /* FIFO Service Request */
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#define PISR __REG(0x40500014) /* PCM In Status Register */
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#define PISR_FIFOE (1 << 4) /* FIFO error */
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#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define PISR_FSR (1 << 2) /* FIFO Service Request */
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#define MCSR __REG(0x40500018) /* Mic In Status Register */
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#define MCSR_FIFOE (1 << 4) /* FIFO error */
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#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define MCSR_FSR (1 << 2) /* FIFO Service Request */
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#define GSR __REG(0x4050001C) /* Global Status Register */
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#define GSR_CDONE (1 << 19) /* Command Done */
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#define GSR_SDONE (1 << 18) /* Status Done */
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#define GSR_RDCS (1 << 15) /* Read Completion Status */
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#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
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#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
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#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
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#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
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#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
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#define GSR_SCR (1 << 9) /* Secondary Codec Ready */
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#define GSR_PCR (1 << 8) /* Primary Codec Ready */
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#define GSR_MCINT (1 << 7) /* Mic In Interrupt */
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#define GSR_POINT (1 << 6) /* PCM Out Interrupt */
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#define GSR_PIINT (1 << 5) /* PCM In Interrupt */
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#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
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#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
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#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
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#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
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#define CAR __REG(0x40500020) /* CODEC Access Register */
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#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
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#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
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#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
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#define MOCR __REG(0x40500100) /* Modem Out Control Register */
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#define MOCR_FEIE (1 << 3) /* FIFO Error */
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#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MICR __REG(0x40500108) /* Modem In Control Register */
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#define MICR_FEIE (1 << 3) /* FIFO Error */
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#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
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#define MOSR __REG(0x40500110) /* Modem Out Status Register */
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#define MOSR_FIFOE (1 << 4) /* FIFO error */
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#define MOSR_FSR (1 << 2) /* FIFO Service Request */
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#define MISR __REG(0x40500118) /* Modem In Status Register */
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#define MISR_FIFOE (1 << 4) /* FIFO error */
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#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
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#define MISR_FSR (1 << 2) /* FIFO Service Request */
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#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
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#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
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#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
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#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
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#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
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/*
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* Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c
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*/
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/*
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* Real Time Clock
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*/
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#define RCNR __REG(0x40900000) /* RTC Count Register */
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#define RTAR __REG(0x40900004) /* RTC Alarm Register */
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#define RTSR __REG(0x40900008) /* RTC Status Register */
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#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
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#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
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#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
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#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
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#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
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#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
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#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
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#define RTSR_AL (1 << 0) /* RTC alarm detected */
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/*
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* OS Timer & Match Registers
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*/
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#define OSMR0 __REG(0x40A00000) /* */
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#define OSMR1 __REG(0x40A00004) /* */
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#define OSMR2 __REG(0x40A00008) /* */
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#define OSMR3 __REG(0x40A0000C) /* */
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#define OSMR4 __REG(0x40A00080) /* */
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#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
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#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
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#define OMCR4 __REG(0x40A000C0) /* */
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#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
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#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
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#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
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#define OSSR_M3 (1 << 3) /* Match status channel 3 */
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#define OSSR_M2 (1 << 2) /* Match status channel 2 */
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#define OSSR_M1 (1 << 1) /* Match status channel 1 */
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#define OSSR_M0 (1 << 0) /* Match status channel 0 */
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#define OWER_WME (1 << 0) /* Watchdog Match Enable */
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#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
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#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
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#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
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#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
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/*
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* Interrupt Controller
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*/
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#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
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#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
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#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
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#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
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#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
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#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
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#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
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#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
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#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
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/*
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* General Purpose I/O
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*/
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#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
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#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
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#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
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#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
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#define GPLR_OFFSET 0x00
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#define GPDR_OFFSET 0x0C
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#define GPSR_OFFSET 0x18
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#define GPCR_OFFSET 0x24
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#define GRER_OFFSET 0x30
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#define GFER_OFFSET 0x3C
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#define GEDR_OFFSET 0x48
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#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
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#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
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#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
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#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
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#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
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#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
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#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
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#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
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#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
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#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
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#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
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#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
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#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
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#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
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#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
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#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
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#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
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#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
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|
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#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
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#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
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#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
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#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
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#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
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#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
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#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
|
|
#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
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|
#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
|
|
#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
|
|
#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
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|
|
|
#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
|
|
#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
|
|
#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
|
|
#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
|
|
#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
|
|
#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
|
|
#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
|
|
|
|
/* More handy macros. The argument is a literal GPIO number. */
|
|
|
|
#define GPIO_bit(x) (1 << ((x) & 0x1f))
|
|
|
|
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
|
|
|
|
/* Interrupt Controller */
|
|
|
|
#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
|
|
#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
|
|
#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
|
|
#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
|
|
#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
|
|
#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
|
|
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
|
|
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
|
|
|
|
#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
|
|
#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
|
|
#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
|
|
#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
|
|
#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
|
|
#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
|
|
#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
|
|
#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
|
|
((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
|
|
#else
|
|
|
|
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
|
|
#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
|
|
#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
|
|
#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
|
|
#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
|
|
#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
|
|
#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
|
|
#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Power Manager - see pxa2xx-regs.h
|
|
*/
|
|
|
|
/*
|
|
* SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
|
|
*/
|
|
|
|
/*
|
|
* MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
|
|
*/
|
|
|
|
/*
|
|
* Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
|
|
*/
|
|
|
|
#endif
|