b1c1759cd1
Per the PIIX4 errata, there maybe a delay between setting the start bit in the Smbus Host Controller Register and the transaction actually starting. If the driver doesn't delay long enough, it may appear that the transaction is complete when actually it hasn't started, this may lead to bus collisions. While 1 ms appears to be enough for most chips, the ServerWorks CSB5 wants 2 ms. Signed-off-by: David Milburn <dmilburn@redhat.com> Signed-off-by: Jean Delvare <khali@linux-fr.org> |
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| .. | ||
| algos | ||
| busses | ||
| chips | ||
| i2c-boardinfo.c | ||
| i2c-core.c | ||
| i2c-core.h | ||
| i2c-dev.c | ||
| Kconfig | ||
| Makefile | ||