589e367f9b
This removes the hardcoded assumption that irq == vector in the msi composition code, and it allows the msi message composition to setup logical mode, or lowest priorirty delivery mode as we do for other apic interrupts, and with the same selection criteria. Basically this moves the problem of what is in the msi message into the architecture irq management code where it belongs. Not in a generic layer that doesn't have enough information to compose msi messages properly. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rajesh Shah <rajesh.shah@intel.com> Cc: Andi Kleen <ak@muc.de> Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
48 lines
1.5 KiB
C
48 lines
1.5 KiB
C
#ifndef ASM_MSIDEF_H
|
|
#define ASM_MSIDEF_H
|
|
|
|
/*
|
|
* Constants for Intel APIC based MSI messages.
|
|
*/
|
|
|
|
/*
|
|
* Shifts for MSI data
|
|
*/
|
|
|
|
#define MSI_DATA_VECTOR_SHIFT 0
|
|
#define MSI_DATA_VECTOR_MASK 0x000000ff
|
|
#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK)
|
|
|
|
#define MSI_DATA_DELIVERY_MODE_SHIFT 8
|
|
#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
|
|
#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
|
|
|
|
#define MSI_DATA_LEVEL_SHIFT 14
|
|
#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
|
|
#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
|
|
|
|
#define MSI_DATA_TRIGGER_SHIFT 15
|
|
#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
|
|
#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
|
|
|
|
/*
|
|
* Shift/mask fields for msi address
|
|
*/
|
|
|
|
#define MSI_ADDR_BASE_HI 0
|
|
#define MSI_ADDR_BASE_LO 0xfee00000
|
|
|
|
#define MSI_ADDR_DEST_MODE_SHIFT 2
|
|
#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
|
|
#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
|
|
|
|
#define MSI_ADDR_REDIRECTION_SHIFT 3
|
|
#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) /* dedicated cpu */
|
|
#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) /* lowest priority */
|
|
|
|
#define MSI_ADDR_DEST_ID_SHIFT 12
|
|
#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
|
|
#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK)
|
|
|
|
#endif /* ASM_MSIDEF_H */
|