3222b36f46
The counter is exported to /sys that keeps track of the number of thermal events, such that the user knows how bad the thermal problem might be (since the logging to syslog and mcelog is rate limited). AK: Fixed cpu hotplug locking Signed-off-by: Dmitriy Zavin <dmitriyz@google.com> Signed-off-by: Andi Kleen <ak@suse.de>
262 lines
6.5 KiB
C
262 lines
6.5 KiB
C
/*
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* P4 specific Machine Check Exception Reporting
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include <asm/apic.h>
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#include <asm/therm_throt.h>
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#include "mce.h"
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/* as supported by the P4/Xeon family */
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struct intel_mce_extended_msrs {
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u32 eax;
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u32 ebx;
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u32 ecx;
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u32 edx;
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u32 esi;
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u32 edi;
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u32 ebp;
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u32 esp;
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u32 eflags;
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u32 eip;
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/* u32 *reserved[]; */
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};
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static int mce_num_extended_msrs = 0;
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#ifdef CONFIG_X86_MCE_P4THERMAL
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static void unexpected_thermal_interrupt(struct pt_regs *regs)
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{
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printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
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smp_processor_id());
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* P4/Xeon Thermal transition interrupt handler */
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static void intel_thermal_interrupt(struct pt_regs *regs)
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{
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__u64 msr_val;
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ack_APIC_irq();
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rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
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therm_throt_process(msr_val & 0x1);
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}
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/* Thermal interrupt handler for this CPU setup */
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static void (*vendor_thermal_interrupt)(struct pt_regs *regs) = unexpected_thermal_interrupt;
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fastcall void smp_thermal_interrupt(struct pt_regs *regs)
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{
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irq_enter();
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vendor_thermal_interrupt(regs);
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irq_exit();
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}
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/* P4/Xeon Thermal regulation detect and init */
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static void intel_init_thermal(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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unsigned int cpu = smp_processor_id();
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/* Thermal monitoring */
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if (!cpu_has(c, X86_FEATURE_ACPI))
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return; /* -ENODEV */
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/* Clock modulation */
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if (!cpu_has(c, X86_FEATURE_ACC))
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return; /* -ENODEV */
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/* first check if its enabled already, in which case there might
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* be some SMM goo which handles it, so we can't even put a handler
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* since it might be delivered via SMI already -zwanem.
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*/
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rdmsr (MSR_IA32_MISC_ENABLE, l, h);
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h = apic_read(APIC_LVTTHMR);
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if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
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printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
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cpu);
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return; /* -EBUSY */
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}
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/* check whether a vector already exists, temporarily masked? */
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if (h & APIC_VECTOR_MASK) {
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printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
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"installed\n",
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cpu, (h & APIC_VECTOR_MASK));
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return; /* -EBUSY */
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}
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/* The temperature transition interrupt handler setup */
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h = THERMAL_APIC_VECTOR; /* our delivery vector */
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h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
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apic_write_around(APIC_LVTTHMR, h);
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rdmsr (MSR_IA32_THERM_INTERRUPT, l, h);
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wrmsr (MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
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/* ok we're good to go... */
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vendor_thermal_interrupt = intel_thermal_interrupt;
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rdmsr (MSR_IA32_MISC_ENABLE, l, h);
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wrmsr (MSR_IA32_MISC_ENABLE, l | (1<<3), h);
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l = apic_read (APIC_LVTTHMR);
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apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
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printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
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/* enable thermal throttle processing */
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atomic_set(&therm_throt_en, 1);
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return;
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}
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#endif /* CONFIG_X86_MCE_P4THERMAL */
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/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
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static inline int intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
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{
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u32 h;
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if (mce_num_extended_msrs == 0)
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goto done;
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rdmsr (MSR_IA32_MCG_EAX, r->eax, h);
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rdmsr (MSR_IA32_MCG_EBX, r->ebx, h);
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rdmsr (MSR_IA32_MCG_ECX, r->ecx, h);
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rdmsr (MSR_IA32_MCG_EDX, r->edx, h);
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rdmsr (MSR_IA32_MCG_ESI, r->esi, h);
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rdmsr (MSR_IA32_MCG_EDI, r->edi, h);
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rdmsr (MSR_IA32_MCG_EBP, r->ebp, h);
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rdmsr (MSR_IA32_MCG_ESP, r->esp, h);
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rdmsr (MSR_IA32_MCG_EFLAGS, r->eflags, h);
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rdmsr (MSR_IA32_MCG_EIP, r->eip, h);
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/* can we rely on kmalloc to do a dynamic
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* allocation for the reserved registers?
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*/
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done:
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return mce_num_extended_msrs;
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}
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static fastcall void intel_machine_check(struct pt_regs * regs, long error_code)
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{
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int recover=1;
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int i;
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struct intel_mce_extended_msrs dbg;
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rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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recover=0;
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printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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if (intel_get_extended_msrs(&dbg)) {
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printk (KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n",
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smp_processor_id(), dbg.eip, dbg.eflags);
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printk (KERN_DEBUG "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n",
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dbg.eax, dbg.ebx, dbg.ecx, dbg.edx);
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printk (KERN_DEBUG "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
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dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
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}
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for (i=0; i<nr_mce_banks; i++) {
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rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
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if (high & (1<<31)) {
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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printk ("[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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printk (" at %08x%08x", ahigh, alow);
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}
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printk ("\n");
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}
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}
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if (recover & 2)
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panic ("CPU context corrupt");
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if (recover & 1)
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panic ("Unable to continue");
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printk(KERN_EMERG "Attempting to continue.\n");
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/*
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* Do not clear the MSR_IA32_MCi_STATUS if the error is not
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* recoverable/continuable.This will allow BIOS to look at the MSRs
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* for errors if the OS could not log the error.
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*/
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for (i=0; i<nr_mce_banks; i++) {
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u32 msr;
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msr = MSR_IA32_MC0_STATUS+i*4;
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rdmsr (msr, low, high);
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if (high&(1<<31)) {
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/* Clear it */
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wrmsr(msr, 0UL, 0UL);
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/* Serialize */
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wmb();
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add_taint(TAINT_MACHINE_CHECK);
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}
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}
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mcgstl &= ~(1<<2);
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wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
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}
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void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int i;
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machine_check_vector = intel_machine_check;
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wmb();
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printk (KERN_INFO "Intel machine check architecture supported.\n");
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rdmsr (MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<8)) /* Control register present ? */
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wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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nr_mce_banks = l & 0xff;
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for (i=0; i<nr_mce_banks; i++) {
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wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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}
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set_in_cr4 (X86_CR4_MCE);
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printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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/* Check for P4/Xeon extended MCE MSRs */
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rdmsr (MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<9)) {/* MCG_EXT_P */
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mce_num_extended_msrs = (l >> 16) & 0xff;
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printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
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" available\n",
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smp_processor_id(), mce_num_extended_msrs);
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#ifdef CONFIG_X86_MCE_P4THERMAL
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/* Check for P4/Xeon Thermal monitor */
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intel_init_thermal(c);
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#endif
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}
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}
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