458eb39d05
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
362 lines
8.8 KiB
C
362 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 Baylibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mdio-mux.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#define ETH_PLL_STS 0x40
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#define ETH_PLL_CTL0 0x44
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#define PLL_CTL0_LOCK_DIG BIT(30)
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#define PLL_CTL0_RST BIT(29)
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#define PLL_CTL0_EN BIT(28)
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#define PLL_CTL0_SEL BIT(23)
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#define PLL_CTL0_N GENMASK(14, 10)
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#define PLL_CTL0_M GENMASK(8, 0)
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#define PLL_LOCK_TIMEOUT 1000000
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#define PLL_MUX_NUM_PARENT 2
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#define ETH_PLL_CTL1 0x48
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#define ETH_PLL_CTL2 0x4c
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#define ETH_PLL_CTL3 0x50
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#define ETH_PLL_CTL4 0x54
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#define ETH_PLL_CTL5 0x58
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#define ETH_PLL_CTL6 0x5c
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#define ETH_PLL_CTL7 0x60
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#define ETH_PHY_CNTL0 0x80
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#define EPHY_G12A_ID 0x33010180
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#define ETH_PHY_CNTL1 0x84
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#define PHY_CNTL1_ST_MODE GENMASK(2, 0)
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#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
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#define EPHY_DFLT_ADD 8
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#define PHY_CNTL1_MII_MODE GENMASK(15, 14)
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#define EPHY_MODE_RMII 0x1
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#define PHY_CNTL1_CLK_EN BIT(16)
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#define PHY_CNTL1_CLKFREQ BIT(17)
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#define PHY_CNTL1_PHY_ENB BIT(18)
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#define ETH_PHY_CNTL2 0x88
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#define PHY_CNTL2_USE_INTERNAL BIT(5)
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#define PHY_CNTL2_SMI_SRC_MAC BIT(6)
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#define PHY_CNTL2_RX_CLK_EPHY BIT(9)
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#define MESON_G12A_MDIO_EXTERNAL_ID 0
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#define MESON_G12A_MDIO_INTERNAL_ID 1
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struct g12a_mdio_mux {
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void __iomem *regs;
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void *mux_handle;
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struct clk *pll;
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};
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struct g12a_ephy_pll {
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void __iomem *base;
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struct clk_hw hw;
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};
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#define g12a_ephy_pll_to_dev(_hw) \
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container_of(_hw, struct g12a_ephy_pll, hw)
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static unsigned long g12a_ephy_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
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u32 val, m, n;
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val = readl(pll->base + ETH_PLL_CTL0);
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m = FIELD_GET(PLL_CTL0_M, val);
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n = FIELD_GET(PLL_CTL0_N, val);
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return parent_rate * m / n;
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}
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static int g12a_ephy_pll_enable(struct clk_hw *hw)
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{
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struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
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u32 val = readl(pll->base + ETH_PLL_CTL0);
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/* Apply both enable an reset */
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val |= PLL_CTL0_RST | PLL_CTL0_EN;
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writel(val, pll->base + ETH_PLL_CTL0);
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/* Clear the reset to let PLL lock */
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val &= ~PLL_CTL0_RST;
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writel(val, pll->base + ETH_PLL_CTL0);
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/* Poll on the digital lock instead of the usual analog lock
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* This is done because bit 31 is unreliable on some SoC. Bit
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* 31 may indicate that the PLL is not lock even though the clock
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* is actually running
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*/
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return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,
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val & PLL_CTL0_LOCK_DIG, 0, PLL_LOCK_TIMEOUT);
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}
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static void g12a_ephy_pll_disable(struct clk_hw *hw)
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{
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struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
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u32 val;
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val = readl(pll->base + ETH_PLL_CTL0);
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val &= ~PLL_CTL0_EN;
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val |= PLL_CTL0_RST;
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writel(val, pll->base + ETH_PLL_CTL0);
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}
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static int g12a_ephy_pll_is_enabled(struct clk_hw *hw)
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{
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struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
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unsigned int val;
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val = readl(pll->base + ETH_PLL_CTL0);
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return (val & PLL_CTL0_LOCK_DIG) ? 1 : 0;
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}
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static int g12a_ephy_pll_init(struct clk_hw *hw)
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{
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struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw);
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/* Apply PLL HW settings */
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writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
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writel(0x927e0000, pll->base + ETH_PLL_CTL1);
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writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
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writel(0x00000000, pll->base + ETH_PLL_CTL3);
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writel(0x00000000, pll->base + ETH_PLL_CTL4);
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writel(0x20200000, pll->base + ETH_PLL_CTL5);
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writel(0x0000c002, pll->base + ETH_PLL_CTL6);
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writel(0x00000023, pll->base + ETH_PLL_CTL7);
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return 0;
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}
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static const struct clk_ops g12a_ephy_pll_ops = {
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.recalc_rate = g12a_ephy_pll_recalc_rate,
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.is_enabled = g12a_ephy_pll_is_enabled,
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.enable = g12a_ephy_pll_enable,
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.disable = g12a_ephy_pll_disable,
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.init = g12a_ephy_pll_init,
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};
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static int g12a_enable_internal_mdio(struct g12a_mdio_mux *priv)
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{
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u32 value;
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int ret;
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/* Enable the phy clock */
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if (!__clk_is_enabled(priv->pll)) {
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ret = clk_prepare_enable(priv->pll);
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if (ret)
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return ret;
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}
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/* Initialize ephy control */
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writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
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/* Make sure we get a 0 -> 1 transition on the enable bit */
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value = FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
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FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
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FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
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PHY_CNTL1_CLK_EN |
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PHY_CNTL1_CLKFREQ;
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writel(value, priv->regs + ETH_PHY_CNTL1);
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writel(PHY_CNTL2_USE_INTERNAL |
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PHY_CNTL2_SMI_SRC_MAC |
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PHY_CNTL2_RX_CLK_EPHY,
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priv->regs + ETH_PHY_CNTL2);
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value |= PHY_CNTL1_PHY_ENB;
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writel(value, priv->regs + ETH_PHY_CNTL1);
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/* The phy needs a bit of time to power up */
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mdelay(10);
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return 0;
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}
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static int g12a_enable_external_mdio(struct g12a_mdio_mux *priv)
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{
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/* Reset the mdio bus mux */
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writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);
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/* Disable the phy clock if enabled */
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if (__clk_is_enabled(priv->pll))
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clk_disable_unprepare(priv->pll);
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return 0;
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}
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static int g12a_mdio_switch_fn(int current_child, int desired_child,
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void *data)
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{
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struct g12a_mdio_mux *priv = dev_get_drvdata(data);
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if (current_child == desired_child)
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return 0;
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switch (desired_child) {
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case MESON_G12A_MDIO_EXTERNAL_ID:
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return g12a_enable_external_mdio(priv);
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case MESON_G12A_MDIO_INTERNAL_ID:
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return g12a_enable_internal_mdio(priv);
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default:
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return -EINVAL;
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}
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}
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static const struct of_device_id g12a_mdio_mux_match[] = {
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{ .compatible = "amlogic,g12a-mdio-mux", },
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{},
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};
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MODULE_DEVICE_TABLE(of, g12a_mdio_mux_match);
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static int g12a_ephy_glue_clk_register(struct device *dev)
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{
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struct g12a_mdio_mux *priv = dev_get_drvdata(dev);
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const char *parent_names[PLL_MUX_NUM_PARENT];
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struct clk_init_data init;
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struct g12a_ephy_pll *pll;
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struct clk_mux *mux;
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struct clk *clk;
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char *name;
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int i;
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/* get the mux parents */
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for (i = 0; i < PLL_MUX_NUM_PARENT; i++) {
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char in_name[8];
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snprintf(in_name, sizeof(in_name), "clkin%d", i);
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clk = devm_clk_get(dev, in_name);
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk),
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"Missing clock %s\n", in_name);
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parent_names[i] = __clk_get_name(clk);
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}
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/* create the input mux */
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mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return -ENOMEM;
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name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev));
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if (!name)
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return -ENOMEM;
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init.name = name;
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init.ops = &clk_mux_ro_ops;
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init.flags = 0;
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init.parent_names = parent_names;
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init.num_parents = PLL_MUX_NUM_PARENT;
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mux->reg = priv->regs + ETH_PLL_CTL0;
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mux->shift = __ffs(PLL_CTL0_SEL);
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mux->mask = PLL_CTL0_SEL >> mux->shift;
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mux->hw.init = &init;
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clk = devm_clk_register(dev, &mux->hw);
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kfree(name);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to register input mux\n");
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return PTR_ERR(clk);
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}
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/* create the pll */
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pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return -ENOMEM;
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name = kasprintf(GFP_KERNEL, "%s#pll", dev_name(dev));
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if (!name)
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return -ENOMEM;
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init.name = name;
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init.ops = &g12a_ephy_pll_ops;
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init.flags = 0;
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parent_names[0] = __clk_get_name(clk);
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init.parent_names = parent_names;
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init.num_parents = 1;
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pll->base = priv->regs;
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pll->hw.init = &init;
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clk = devm_clk_register(dev, &pll->hw);
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kfree(name);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to register input mux\n");
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return PTR_ERR(clk);
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}
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priv->pll = clk;
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return 0;
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}
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static int g12a_mdio_mux_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct g12a_mdio_mux *priv;
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struct clk *pclk;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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priv->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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pclk = devm_clk_get_enabled(dev, "pclk");
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if (IS_ERR(pclk))
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return dev_err_probe(dev, PTR_ERR(pclk),
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"failed to get peripheral clock\n");
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/* Register PLL in CCF */
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ret = g12a_ephy_glue_clk_register(dev);
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if (ret)
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return ret;
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ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn,
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&priv->mux_handle, dev, NULL);
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if (ret)
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dev_err_probe(dev, ret, "mdio multiplexer init failed\n");
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return ret;
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}
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static void g12a_mdio_mux_remove(struct platform_device *pdev)
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{
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struct g12a_mdio_mux *priv = platform_get_drvdata(pdev);
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mdio_mux_uninit(priv->mux_handle);
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if (__clk_is_enabled(priv->pll))
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clk_disable_unprepare(priv->pll);
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}
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static struct platform_driver g12a_mdio_mux_driver = {
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.probe = g12a_mdio_mux_probe,
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.remove_new = g12a_mdio_mux_remove,
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.driver = {
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.name = "g12a-mdio_mux",
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.of_match_table = g12a_mdio_mux_match,
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},
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};
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module_platform_driver(g12a_mdio_mux_driver);
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MODULE_DESCRIPTION("Amlogic G12a MDIO multiplexer driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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