faf0678ec8
Add the definitions of GSI register offsets and fields for IPA v5.0. These are used for the SDX65 SoC. Increase the maximum channel and event ring counts supported by the driver, so those implemented by the SDX65 are supported. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
384 lines
9.7 KiB
C
384 lines
9.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2018-2023 Linaro Ltd.
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*/
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#ifndef _GSI_REG_H_
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#define _GSI_REG_H_
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/* === Only "gsi.c" and "gsi_reg.c" should include this file === */
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#include <linux/bits.h>
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struct platform_device;
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struct gsi;
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/**
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* DOC: GSI Registers
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*
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* GSI registers are located within the "gsi" address space defined by Device
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* Tree. The offset of each register within that space is specified by
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* symbols defined below. The GSI address space is mapped to virtual memory
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* space in gsi_init(). All GSI registers are 32 bits wide.
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*
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* Each register type is duplicated for a number of instances of something.
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* For example, each GSI channel has its own set of registers defining its
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* configuration. The offset to a channel's set of registers is computed
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* based on a "base" offset plus an additional "stride" amount computed
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* from the channel's ID. For such registers, the offset is computed by a
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* function-like macro that takes a parameter used in the computation.
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*
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* The offset of a register dependent on execution environment is computed
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* by a macro that is supplied a parameter "ee". The "ee" value is a member
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* of the gsi_ee_id enumerated type.
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*
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* The offset of a channel register is computed by a macro that is supplied a
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* parameter "ch". The "ch" value is a channel id whose maximum value is 30
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* (though the actual limit is hardware-dependent).
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*
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* The offset of an event register is computed by a macro that is supplied a
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* parameter "ev". The "ev" value is an event id whose maximum value is 15
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* (though the actual limit is hardware-dependent).
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*/
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/* enum gsi_reg_id - GSI register IDs */
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enum gsi_reg_id {
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INTER_EE_SRC_CH_IRQ_MSK, /* IPA v3.5+ */
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INTER_EE_SRC_EV_CH_IRQ_MSK, /* IPA v3.5+ */
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CH_C_CNTXT_0,
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CH_C_CNTXT_1,
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CH_C_CNTXT_2,
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CH_C_CNTXT_3,
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CH_C_QOS,
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CH_C_SCRATCH_0,
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CH_C_SCRATCH_1,
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CH_C_SCRATCH_2,
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CH_C_SCRATCH_3,
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EV_CH_E_CNTXT_0,
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EV_CH_E_CNTXT_1,
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EV_CH_E_CNTXT_2,
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EV_CH_E_CNTXT_3,
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EV_CH_E_CNTXT_4,
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EV_CH_E_CNTXT_8,
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EV_CH_E_CNTXT_9,
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EV_CH_E_CNTXT_10,
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EV_CH_E_CNTXT_11,
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EV_CH_E_CNTXT_12,
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EV_CH_E_CNTXT_13,
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EV_CH_E_SCRATCH_0,
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EV_CH_E_SCRATCH_1,
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CH_C_DOORBELL_0,
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EV_CH_E_DOORBELL_0,
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GSI_STATUS,
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CH_CMD,
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EV_CH_CMD,
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GENERIC_CMD,
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HW_PARAM_2, /* IPA v3.5.1+ */
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HW_PARAM_4, /* IPA v5.0+ */
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CNTXT_TYPE_IRQ,
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CNTXT_TYPE_IRQ_MSK,
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CNTXT_SRC_CH_IRQ,
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CNTXT_SRC_CH_IRQ_MSK,
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CNTXT_SRC_CH_IRQ_CLR,
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CNTXT_SRC_EV_CH_IRQ,
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CNTXT_SRC_EV_CH_IRQ_MSK,
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CNTXT_SRC_EV_CH_IRQ_CLR,
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CNTXT_SRC_IEOB_IRQ,
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CNTXT_SRC_IEOB_IRQ_MSK,
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CNTXT_SRC_IEOB_IRQ_CLR,
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CNTXT_GLOB_IRQ_STTS,
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CNTXT_GLOB_IRQ_EN,
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CNTXT_GLOB_IRQ_CLR,
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CNTXT_GSI_IRQ_STTS,
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CNTXT_GSI_IRQ_EN,
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CNTXT_GSI_IRQ_CLR,
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CNTXT_INTSET,
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ERROR_LOG,
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ERROR_LOG_CLR,
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CNTXT_SCRATCH_0,
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GSI_REG_ID_COUNT, /* Last; not an ID */
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};
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/* CH_C_CNTXT_0 register */
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enum gsi_reg_ch_c_cntxt_0_field_id {
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CHTYPE_PROTOCOL,
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CHTYPE_DIR,
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CH_EE,
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CHID,
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CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */
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ERINDEX, /* Not IPA v5.0+ */
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CHSTATE,
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ELEMENT_SIZE,
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};
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/** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */
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enum gsi_channel_type {
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GSI_CHANNEL_TYPE_MHI = 0x0,
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GSI_CHANNEL_TYPE_XHCI = 0x1,
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GSI_CHANNEL_TYPE_GPI = 0x2,
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GSI_CHANNEL_TYPE_XDCI = 0x3,
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GSI_CHANNEL_TYPE_WDI2 = 0x4,
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GSI_CHANNEL_TYPE_GCI = 0x5,
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GSI_CHANNEL_TYPE_WDI3 = 0x6,
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GSI_CHANNEL_TYPE_MHIP = 0x7,
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GSI_CHANNEL_TYPE_AQC = 0x8,
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GSI_CHANNEL_TYPE_11AD = 0x9,
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};
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/* CH_C_CNTXT_1 register */
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enum gsi_reg_ch_c_cntxt_1_field_id {
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CH_R_LENGTH,
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CH_ERINDEX, /* IPA v5.0+ */
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};
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/* CH_C_QOS register */
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enum gsi_reg_ch_c_qos_field_id {
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WRR_WEIGHT,
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MAX_PREFETCH,
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USE_DB_ENG,
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USE_ESCAPE_BUF_ONLY, /* IPA v4.0-4.2 */
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PREFETCH_MODE, /* IPA v4.5+ */
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EMPTY_LVL_THRSHOLD, /* IPA v4.5+ */
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DB_IN_BYTES, /* IPA v4.9+ */
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LOW_LATENCY_EN, /* IPA v5.0+ */
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};
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/** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */
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enum gsi_prefetch_mode {
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USE_PREFETCH_BUFS = 0,
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ESCAPE_BUF_ONLY = 1,
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SMART_PREFETCH = 2,
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FREE_PREFETCH = 3,
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};
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/* EV_CH_E_CNTXT_0 register */
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enum gsi_reg_ch_c_ev_ch_e_cntxt_0_field_id {
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EV_CHTYPE, /* enum gsi_channel_type */
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EV_EE, /* enum gsi_ee_id; always GSI_EE_AP for us */
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EV_EVCHID,
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EV_INTYPE,
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EV_CHSTATE,
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EV_ELEMENT_SIZE,
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};
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/* EV_CH_E_CNTXT_1 register */
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enum gsi_reg_ev_ch_c_cntxt_1_field_id {
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R_LENGTH,
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};
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/* EV_CH_E_CNTXT_8 register */
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enum gsi_reg_ch_c_ev_ch_e_cntxt_8_field_id {
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EV_MODT,
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EV_MODC,
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EV_MOD_CNT,
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};
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/* GSI_STATUS register */
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enum gsi_reg_gsi_status_field_id {
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ENABLED,
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};
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/* CH_CMD register */
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enum gsi_reg_gsi_ch_cmd_field_id {
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CH_CHID,
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CH_OPCODE,
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};
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/** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */
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enum gsi_ch_cmd_opcode {
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GSI_CH_ALLOCATE = 0x0,
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GSI_CH_START = 0x1,
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GSI_CH_STOP = 0x2,
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GSI_CH_RESET = 0x9,
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GSI_CH_DE_ALLOC = 0xa,
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GSI_CH_DB_STOP = 0xb,
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};
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/* EV_CH_CMD register */
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enum gsi_ev_ch_cmd_field_id {
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EV_CHID,
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EV_OPCODE,
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};
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/** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */
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enum gsi_evt_cmd_opcode {
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GSI_EVT_ALLOCATE = 0x0,
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GSI_EVT_RESET = 0x9,
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GSI_EVT_DE_ALLOC = 0xa,
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};
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/* GENERIC_CMD register */
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enum gsi_generic_cmd_field_id {
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GENERIC_OPCODE,
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GENERIC_CHID,
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GENERIC_EE,
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GENERIC_PARAMS, /* IPA v4.11+ */
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};
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/** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */
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enum gsi_generic_cmd_opcode {
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GSI_GENERIC_HALT_CHANNEL = 0x1,
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GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
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GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */
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GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */
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GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */
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};
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/* HW_PARAM_2 register */ /* IPA v3.5.1+ */
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enum gsi_hw_param_2_field_id {
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IRAM_SIZE,
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NUM_CH_PER_EE,
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NUM_EV_PER_EE, /* Not IPA v5.0+ */
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GSI_CH_PEND_TRANSLATE,
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GSI_CH_FULL_LOGIC,
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GSI_USE_SDMA, /* IPA v4.0+ */
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GSI_SDMA_N_INT, /* IPA v4.0+ */
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GSI_SDMA_MAX_BURST, /* IPA v4.0+ */
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GSI_SDMA_N_IOVEC, /* IPA v4.0+ */
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GSI_USE_RD_WR_ENG, /* IPA v4.2+ */
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GSI_USE_INTER_EE, /* IPA v4.2+ */
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};
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/** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */
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enum gsi_iram_size {
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IRAM_SIZE_ONE_KB = 0x0,
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IRAM_SIZE_TWO_KB = 0x1,
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/* The next two values are available for IPA v4.0 and above */
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IRAM_SIZE_TWO_N_HALF_KB = 0x2,
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IRAM_SIZE_THREE_KB = 0x3,
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/* The next two values are available for IPA v4.5 and above */
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IRAM_SIZE_THREE_N_HALF_KB = 0x4,
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IRAM_SIZE_FOUR_KB = 0x5,
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};
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/* HW_PARAM_4 register */ /* IPA v5.0+ */
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enum gsi_hw_param_4_field_id {
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EV_PER_EE,
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IRAM_PROTOCOL_COUNT,
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};
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/**
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* enum gsi_irq_type_id: GSI IRQ types
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* @GSI_CH_CTRL: Channel allocation, deallocation, etc.
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* @GSI_EV_CTRL: Event ring allocation, deallocation, etc.
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* @GSI_GLOB_EE: Global/general event
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* @GSI_IEOB: Transfer (TRE) completion
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* @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused)
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* @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused)
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* @GSI_GENERAL: General hardware event (bus error, etc.)
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*/
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enum gsi_irq_type_id {
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GSI_CH_CTRL = BIT(0),
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GSI_EV_CTRL = BIT(1),
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GSI_GLOB_EE = BIT(2),
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GSI_IEOB = BIT(3),
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GSI_INTER_EE_CH_CTRL = BIT(4),
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GSI_INTER_EE_EV_CTRL = BIT(5),
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GSI_GENERAL = BIT(6),
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/* IRQ types 7-31 (and their bit values) are reserved */
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};
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/** enum gsi_global_irq_id: Global GSI interrupt events */
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enum gsi_global_irq_id {
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ERROR_INT = BIT(0),
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GP_INT1 = BIT(1),
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GP_INT2 = BIT(2),
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GP_INT3 = BIT(3),
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/* Global IRQ types 4-31 (and their bit values) are reserved */
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};
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/** enum gsi_general_irq_id: GSI general IRQ conditions */
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enum gsi_general_irq_id {
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BREAK_POINT = BIT(0),
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BUS_ERROR = BIT(1),
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CMD_FIFO_OVRFLOW = BIT(2),
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MCS_STACK_OVRFLOW = BIT(3),
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/* General IRQ types 4-31 (and their bit values) are reserved */
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};
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/* CNTXT_INTSET register */
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enum gsi_cntxt_intset_field_id {
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INTYPE,
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};
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/* ERROR_LOG register */
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enum gsi_error_log_field_id {
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ERR_ARG3,
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ERR_ARG2,
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ERR_ARG1,
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ERR_CODE,
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ERR_VIRT_IDX,
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ERR_TYPE,
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ERR_EE,
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};
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/** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */
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enum gsi_err_code {
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GSI_INVALID_TRE = 0x1,
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GSI_OUT_OF_BUFFERS = 0x2,
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GSI_OUT_OF_RESOURCES = 0x3,
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GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
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GSI_EVT_RING_EMPTY = 0x5,
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GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
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/* 7 is not assigned */
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GSI_HWO_1 = 0x8,
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};
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/** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */
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enum gsi_err_type {
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GSI_ERR_TYPE_GLOB = 0x1,
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GSI_ERR_TYPE_CHAN = 0x2,
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GSI_ERR_TYPE_EVT = 0x3,
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};
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/* CNTXT_SCRATCH_0 register */
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enum gsi_cntxt_scratch_0_field_id {
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INTER_EE_RESULT,
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GENERIC_EE_RESULT,
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};
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/** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */
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enum gsi_generic_ee_result {
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GENERIC_EE_SUCCESS = 0x1,
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GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2,
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GENERIC_EE_INCORRECT_DIRECTION = 0x3,
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GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
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GENERIC_EE_INCORRECT_CHANNEL = 0x5,
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GENERIC_EE_RETRY = 0x6,
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GENERIC_EE_NO_RESOURCES = 0x7,
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};
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extern const struct regs gsi_regs_v3_1;
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extern const struct regs gsi_regs_v3_5_1;
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extern const struct regs gsi_regs_v4_0;
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extern const struct regs gsi_regs_v4_5;
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extern const struct regs gsi_regs_v4_9;
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extern const struct regs gsi_regs_v4_11;
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extern const struct regs gsi_regs_v5_0;
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/**
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* gsi_reg() - Return the structure describing a GSI register
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* @gsi: GSI pointer
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* @reg_id: GSI register ID
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*/
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const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id);
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/**
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* gsi_reg_init() - Perform GSI register initialization
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* @gsi: GSI pointer
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* @pdev: GSI (IPA) platform device
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*
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* Initialize GSI registers, including looking up and I/O mapping
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* the "gsi" memory space.
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*/
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int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev);
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/**
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* gsi_reg_exit() - Inverse of gsi_reg_init()
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* @gsi: GSI pointer
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*/
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void gsi_reg_exit(struct gsi *gsi);
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#endif /* _GSI_REG_H_ */
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