e995fcde60
The VT-d specification has removed architectural support of the requests with pasid with a value of 1 for Execute-Requested (ER). And the NXE bit in the pasid table entry and XD bit in the first-stage paging Entries are deprecated accordingly. Remove the programming of these bits to make it consistent with the spec. Suggested-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Link: https://lore.kernel.org/r/20240624032351.249858-1-baolu.lu@linux.intel.com Link: https://lore.kernel.org/r/20240702130839.108139-4-baolu.lu@linux.intel.com Signed-off-by: Will Deacon <will@kernel.org>
314 lines
7.9 KiB
C
314 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* pasid.h - PASID idr, table and entry header
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*
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* Copyright (C) 2018 Intel Corporation
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*
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* Author: Lu Baolu <baolu.lu@linux.intel.com>
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*/
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#ifndef __INTEL_PASID_H
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#define __INTEL_PASID_H
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#define PASID_MAX 0x100000
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#define PASID_PTE_MASK 0x3F
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#define PASID_PTE_PRESENT 1
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#define PASID_PTE_FPD 2
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#define PDE_PFN_MASK PAGE_MASK
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#define PASID_PDE_SHIFT 6
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#define MAX_NR_PASID_BITS 20
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#define PASID_TBL_ENTRIES BIT(PASID_PDE_SHIFT)
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#define is_pasid_enabled(entry) (((entry)->lo >> 3) & 0x1)
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#define get_pasid_dir_size(entry) (1 << ((((entry)->lo >> 9) & 0x7) + 7))
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/*
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* Domain ID reserved for pasid entries programmed for first-level
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* only and pass-through transfer modes.
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*/
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#define FLPT_DEFAULT_DID 1
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#define NUM_RESERVED_DID 2
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#define PASID_FLAG_NESTED BIT(1)
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#define PASID_FLAG_PAGE_SNOOP BIT(2)
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/*
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* The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
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* level translation, otherwise, 4-level paging will be used.
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*/
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#define PASID_FLAG_FL5LP BIT(1)
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struct pasid_dir_entry {
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u64 val;
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};
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struct pasid_entry {
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u64 val[8];
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};
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#define PASID_ENTRY_PGTT_FL_ONLY (1)
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#define PASID_ENTRY_PGTT_SL_ONLY (2)
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#define PASID_ENTRY_PGTT_NESTED (3)
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#define PASID_ENTRY_PGTT_PT (4)
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/* The representative of a PASID table */
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struct pasid_table {
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void *table; /* pasid table pointer */
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int order; /* page order of pasid table */
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u32 max_pasid; /* max pasid */
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};
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/* Get PRESENT bit of a PASID directory entry. */
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static inline bool pasid_pde_is_present(struct pasid_dir_entry *pde)
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{
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return READ_ONCE(pde->val) & PASID_PTE_PRESENT;
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}
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/* Get PASID table from a PASID directory entry. */
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static inline struct pasid_entry *
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get_pasid_table_from_pde(struct pasid_dir_entry *pde)
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{
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if (!pasid_pde_is_present(pde))
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return NULL;
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return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK);
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}
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/* Get PRESENT bit of a PASID table entry. */
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static inline bool pasid_pte_is_present(struct pasid_entry *pte)
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{
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return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT;
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}
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/* Get PGTT field of a PASID table entry */
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static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte)
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{
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return (u16)((READ_ONCE(pte->val[0]) >> 6) & 0x7);
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}
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static inline void pasid_clear_entry(struct pasid_entry *pe)
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{
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WRITE_ONCE(pe->val[0], 0);
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WRITE_ONCE(pe->val[1], 0);
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WRITE_ONCE(pe->val[2], 0);
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WRITE_ONCE(pe->val[3], 0);
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WRITE_ONCE(pe->val[4], 0);
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WRITE_ONCE(pe->val[5], 0);
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WRITE_ONCE(pe->val[6], 0);
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WRITE_ONCE(pe->val[7], 0);
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}
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static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe)
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{
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WRITE_ONCE(pe->val[0], PASID_PTE_FPD);
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WRITE_ONCE(pe->val[1], 0);
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WRITE_ONCE(pe->val[2], 0);
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WRITE_ONCE(pe->val[3], 0);
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WRITE_ONCE(pe->val[4], 0);
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WRITE_ONCE(pe->val[5], 0);
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WRITE_ONCE(pe->val[6], 0);
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WRITE_ONCE(pe->val[7], 0);
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}
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static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)
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{
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u64 old;
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old = READ_ONCE(*ptr);
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WRITE_ONCE(*ptr, (old & ~mask) | bits);
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}
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static inline u64 pasid_get_bits(u64 *ptr)
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{
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return READ_ONCE(*ptr);
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}
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/*
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* Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode
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* PASID entry.
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*/
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static inline void
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pasid_set_domain_id(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
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}
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/*
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* Get domain ID value of a scalable mode PASID entry.
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*/
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static inline u16
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pasid_get_domain_id(struct pasid_entry *pe)
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{
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return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
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}
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/*
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* Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)
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* of a scalable mode PASID entry.
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*/
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static inline void
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pasid_set_slptr(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
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}
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/*
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* Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID
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* entry.
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*/
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static inline void
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pasid_set_address_width(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
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}
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/*
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* Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)
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* of a scalable mode PASID entry.
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*/
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static inline void
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pasid_set_translation_type(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
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}
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/*
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* Enable fault processing by clearing the FPD(Fault Processing
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* Disable) field (Bit 1) of a scalable mode PASID entry.
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*/
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static inline void pasid_set_fault_enable(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[0], 1 << 1, 0);
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}
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/*
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* Enable second level A/D bits by setting the SLADE (Second Level
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* Access Dirty Enable) field (Bit 9) of a scalable mode PASID
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* entry.
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*/
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static inline void pasid_set_ssade(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[0], 1 << 9, 1 << 9);
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}
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/*
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* Disable second level A/D bits by clearing the SLADE (Second Level
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* Access Dirty Enable) field (Bit 9) of a scalable mode PASID
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* entry.
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*/
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static inline void pasid_clear_ssade(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[0], 1 << 9, 0);
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}
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/*
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* Checks if second level A/D bits specifically the SLADE (Second Level
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* Access Dirty Enable) field (Bit 9) of a scalable mode PASID
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* entry is set.
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*/
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static inline bool pasid_get_ssade(struct pasid_entry *pe)
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{
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return pasid_get_bits(&pe->val[0]) & (1 << 9);
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}
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/*
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* Setup the SRE(Supervisor Request Enable) field (Bit 128) of a
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* scalable mode PASID entry.
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*/
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static inline void pasid_set_sre(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[2], 1 << 0, 1);
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}
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/*
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* Setup the WPE(Write Protect Enable) field (Bit 132) of a
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* scalable mode PASID entry.
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*/
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static inline void pasid_set_wpe(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4);
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}
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/*
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* Setup the P(Present) field (Bit 0) of a scalable mode PASID
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* entry.
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*/
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static inline void pasid_set_present(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[0], 1 << 0, 1);
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}
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/*
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* Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID
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* entry.
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*/
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static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
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{
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pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
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}
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/*
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* Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode
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* PASID entry.
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*/
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static inline void
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pasid_set_pgsnp(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[1], 1ULL << 24, 1ULL << 24);
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}
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/*
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* Setup the First Level Page table Pointer field (Bit 140~191)
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* of a scalable mode PASID entry.
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*/
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static inline void
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pasid_set_flptr(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
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}
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/*
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* Setup the First Level Paging Mode field (Bit 130~131) of a
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* scalable mode PASID entry.
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*/
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static inline void
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pasid_set_flpm(struct pasid_entry *pe, u64 value)
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{
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pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
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}
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/*
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* Setup the Extended Access Flag Enable (EAFE) field (Bit 135)
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* of a scalable mode PASID entry.
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*/
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static inline void pasid_set_eafe(struct pasid_entry *pe)
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{
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pasid_set_bits(&pe->val[2], 1 << 7, 1 << 7);
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}
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extern unsigned int intel_pasid_max_id;
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int intel_pasid_alloc_table(struct device *dev);
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void intel_pasid_free_table(struct device *dev);
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struct pasid_table *intel_pasid_get_table(struct device *dev);
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int intel_pasid_setup_first_level(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd,
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u32 pasid, u16 did, int flags);
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int intel_pasid_setup_second_level(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, u32 pasid);
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int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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bool enabled);
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int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
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struct device *dev, u32 pasid);
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int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev,
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u32 pasid, struct dmar_domain *domain);
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void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
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struct device *dev, u32 pasid,
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bool fault_ignore);
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void intel_pasid_setup_page_snoop_control(struct intel_iommu *iommu,
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struct device *dev, u32 pasid);
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int intel_pasid_setup_sm_context(struct device *dev);
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void intel_pasid_teardown_sm_context(struct device *dev);
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#endif /* __INTEL_PASID_H */
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