7fdf9b05c7
DPPA2(Data Path Acceleration Architecture 2) qDMA supports virtualized channel by allowing DMA jobs to be enqueued into different work queues. Core can initiate a DMA transaction by preparing a frame descriptor(FD) for each DMA job and enqueuing this job through a hardware portal. DPAA2 components can also prepare a FD and enqueue a DMA job through a hardware portal. The qDMA prefetches DMA jobs through DPAA2 hardware portal. It then schedules and dispatches to internal DMA hardware engines, which generate read and write requests. Both qDMA source data and destination data can be either contiguous or non-contiguous using one or more scatter/gather tables. The qDMA supports global bandwidth flow control where all DMA transactions are stalled if the bandwidth threshold has been reached. Also supported are transaction based read throttling. Add NXP dppa2 qDMA to support some of Layerscape SoCs. such as: LS1088A, LS208xA, LX2, etc. Signed-off-by: Peng Ma <peng.ma@nxp.com> Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
10 lines
253 B
Plaintext
10 lines
253 B
Plaintext
menuconfig FSL_DPAA2_QDMA
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tristate "NXP DPAA2 QDMA"
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depends on ARM64
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depends on FSL_MC_BUS && FSL_MC_DPIO
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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NXP Data Path Acceleration Architecture 2 QDMA driver,
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using the NXP MC bus driver.
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