9f93a0a428
The previous wrapper qcom_cc_really_probe takes the platform device as parameter, which is limited to platform driver. As for qca8k clock controller driver, which is registered as the MDIO device, which also follows the qcom clock framework. To commonize qcom_cc_really_probe, updating it to take the struct device as parameter, so that the qcom_cc_really_probe can be utilized by the previous platform device and the new added MDIO device. Also update the current clock controller drivers to take &pdev->dev as parameter when calling qcom_cc_really_probe. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Link: https://lore.kernel.org/r/20240605124541.2711467-4-quic_luoj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
194 lines
4.6 KiB
C
194 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022, Linaro Limited
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "reset.h"
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enum {
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DT_BI_TCXO_PAD,
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};
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static struct clk_branch tcsr_pcie_0_clkref_en = {
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.halt_reg = 0x15100,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15100,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_pcie_1_clkref_en = {
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.halt_reg = 0x15114,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15114,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_pcie_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_ufs_clkref_en = {
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.halt_reg = 0x15110,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15110,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_ufs_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_ufs_pad_clkref_en = {
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.halt_reg = 0x15104,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15104,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_ufs_pad_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb2_clkref_en = {
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.halt_reg = 0x15118,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15118,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb2_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_usb3_clkref_en = {
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.halt_reg = 0x15108,
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x15108,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "tcsr_usb3_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *tcsr_cc_sm8550_clocks[] = {
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[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
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[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
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[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
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[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
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[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
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[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
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};
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static const struct regmap_config tcsr_cc_sm8550_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x2f000,
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.fast_io = true,
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};
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static const struct qcom_cc_desc tcsr_cc_sm8550_desc = {
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.config = &tcsr_cc_sm8550_regmap_config,
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.clks = tcsr_cc_sm8550_clocks,
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.num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks),
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};
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static const struct of_device_id tcsr_cc_sm8550_match_table[] = {
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{ .compatible = "qcom,sm8550-tcsr" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table);
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static int tcsr_cc_sm8550_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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return qcom_cc_really_probe(&pdev->dev, &tcsr_cc_sm8550_desc, regmap);
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}
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static struct platform_driver tcsr_cc_sm8550_driver = {
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.probe = tcsr_cc_sm8550_probe,
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.driver = {
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.name = "tcsr_cc-sm8550",
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.of_match_table = tcsr_cc_sm8550_match_table,
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},
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};
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static int __init tcsr_cc_sm8550_init(void)
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{
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return platform_driver_register(&tcsr_cc_sm8550_driver);
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}
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subsys_initcall(tcsr_cc_sm8550_init);
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static void __exit tcsr_cc_sm8550_exit(void)
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{
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platform_driver_unregister(&tcsr_cc_sm8550_driver);
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}
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module_exit(tcsr_cc_sm8550_exit);
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MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver");
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MODULE_LICENSE("GPL");
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