c8c655c34e
* More phys_to_virt conversions
* Improvement of AP management for VSIE (nested virtualization)
ARM64:
* Numerous fixes for the pathological lock inversion issue that
plagued KVM/arm64 since... forever.
* New framework allowing SMCCC-compliant hypercalls to be forwarded
to userspace, hopefully paving the way for some more features
being moved to VMMs rather than be implemented in the kernel.
* Large rework of the timer code to allow a VM-wide offset to be
applied to both virtual and physical counters as well as a
per-timer, per-vcpu offset that complements the global one.
This last part allows the NV timer code to be implemented on
top.
* A small set of fixes to make sure that we don't change anything
affecting the EL1&0 translation regime just after having having
taken an exception to EL2 until we have executed a DSB. This
ensures that speculative walks started in EL1&0 have completed.
* The usual selftest fixes and improvements.
KVM x86 changes for 6.4:
* Optimize CR0.WP toggling by avoiding an MMU reload when TDP is enabled,
and by giving the guest control of CR0.WP when EPT is enabled on VMX
(VMX-only because SVM doesn't support per-bit controls)
* Add CR0/CR4 helpers to query single bits, and clean up related code
where KVM was interpreting kvm_read_cr4_bits()'s "unsigned long" return
as a bool
* Move AMD_PSFD to cpufeatures.h and purge KVM's definition
* Avoid unnecessary writes+flushes when the guest is only adding new PTEs
* Overhaul .sync_page() and .invlpg() to utilize .sync_page()'s optimizations
when emulating invalidations
* Clean up the range-based flushing APIs
* Revamp the TDP MMU's reaping of Accessed/Dirty bits to clear a single
A/D bit using a LOCK AND instead of XCHG, and skip all of the "handle
changed SPTE" overhead associated with writing the entire entry
* Track the number of "tail" entries in a pte_list_desc to avoid having
to walk (potentially) all descriptors during insertion and deletion,
which gets quite expensive if the guest is spamming fork()
* Disallow virtualizing legacy LBRs if architectural LBRs are available,
the two are mutually exclusive in hardware
* Disallow writes to immutable feature MSRs (notably PERF_CAPABILITIES)
after KVM_RUN, similar to CPUID features
* Overhaul the vmx_pmu_caps selftest to better validate PERF_CAPABILITIES
* Apply PMU filters to emulated events and add test coverage to the
pmu_event_filter selftest
x86 AMD:
* Add support for virtual NMIs
* Fixes for edge cases related to virtual interrupts
x86 Intel:
* Don't advertise XTILE_CFG in KVM_GET_SUPPORTED_CPUID if XTILE_DATA is
not being reported due to userspace not opting in via prctl()
* Fix a bug in emulation of ENCLS in compatibility mode
* Allow emulation of NOP and PAUSE for L2
* AMX selftests improvements
* Misc cleanups
MIPS:
* Constify MIPS's internal callbacks (a leftover from the hardware enabling
rework that landed in 6.3)
Generic:
* Drop unnecessary casts from "void *" throughout kvm_main.c
* Tweak the layout of "struct kvm_mmu_memory_cache" to shrink the struct
size by 8 bytes on 64-bit kernels by utilizing a padding hole
Documentation:
* Fix goof introduced by the conversion to rST
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"s390:
- More phys_to_virt conversions
- Improvement of AP management for VSIE (nested virtualization)
ARM64:
- Numerous fixes for the pathological lock inversion issue that
plagued KVM/arm64 since... forever.
- New framework allowing SMCCC-compliant hypercalls to be forwarded
to userspace, hopefully paving the way for some more features being
moved to VMMs rather than be implemented in the kernel.
- Large rework of the timer code to allow a VM-wide offset to be
applied to both virtual and physical counters as well as a
per-timer, per-vcpu offset that complements the global one. This
last part allows the NV timer code to be implemented on top.
- A small set of fixes to make sure that we don't change anything
affecting the EL1&0 translation regime just after having having
taken an exception to EL2 until we have executed a DSB. This
ensures that speculative walks started in EL1&0 have completed.
- The usual selftest fixes and improvements.
x86:
- Optimize CR0.WP toggling by avoiding an MMU reload when TDP is
enabled, and by giving the guest control of CR0.WP when EPT is
enabled on VMX (VMX-only because SVM doesn't support per-bit
controls)
- Add CR0/CR4 helpers to query single bits, and clean up related code
where KVM was interpreting kvm_read_cr4_bits()'s "unsigned long"
return as a bool
- Move AMD_PSFD to cpufeatures.h and purge KVM's definition
- Avoid unnecessary writes+flushes when the guest is only adding new
PTEs
- Overhaul .sync_page() and .invlpg() to utilize .sync_page()'s
optimizations when emulating invalidations
- Clean up the range-based flushing APIs
- Revamp the TDP MMU's reaping of Accessed/Dirty bits to clear a
single A/D bit using a LOCK AND instead of XCHG, and skip all of
the "handle changed SPTE" overhead associated with writing the
entire entry
- Track the number of "tail" entries in a pte_list_desc to avoid
having to walk (potentially) all descriptors during insertion and
deletion, which gets quite expensive if the guest is spamming
fork()
- Disallow virtualizing legacy LBRs if architectural LBRs are
available, the two are mutually exclusive in hardware
- Disallow writes to immutable feature MSRs (notably
PERF_CAPABILITIES) after KVM_RUN, similar to CPUID features
- Overhaul the vmx_pmu_caps selftest to better validate
PERF_CAPABILITIES
- Apply PMU filters to emulated events and add test coverage to the
pmu_event_filter selftest
- AMD SVM:
- Add support for virtual NMIs
- Fixes for edge cases related to virtual interrupts
- Intel AMX:
- Don't advertise XTILE_CFG in KVM_GET_SUPPORTED_CPUID if
XTILE_DATA is not being reported due to userspace not opting in
via prctl()
- Fix a bug in emulation of ENCLS in compatibility mode
- Allow emulation of NOP and PAUSE for L2
- AMX selftests improvements
- Misc cleanups
MIPS:
- Constify MIPS's internal callbacks (a leftover from the hardware
enabling rework that landed in 6.3)
Generic:
- Drop unnecessary casts from "void *" throughout kvm_main.c
- Tweak the layout of "struct kvm_mmu_memory_cache" to shrink the
struct size by 8 bytes on 64-bit kernels by utilizing a padding
hole
Documentation:
- Fix goof introduced by the conversion to rST"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (211 commits)
KVM: s390: pci: fix virtual-physical confusion on module unload/load
KVM: s390: vsie: clarifications on setting the APCB
KVM: s390: interrupt: fix virtual-physical confusion for next alert GISA
KVM: arm64: Have kvm_psci_vcpu_on() use WRITE_ONCE() to update mp_state
KVM: arm64: Acquire mp_state_lock in kvm_arch_vcpu_ioctl_vcpu_init()
KVM: selftests: Test the PMU event "Instructions retired"
KVM: selftests: Copy full counter values from guest in PMU event filter test
KVM: selftests: Use error codes to signal errors in PMU event filter test
KVM: selftests: Print detailed info in PMU event filter asserts
KVM: selftests: Add helpers for PMC asserts in PMU event filter test
KVM: selftests: Add a common helper for the PMU event filter guest code
KVM: selftests: Fix spelling mistake "perrmited" -> "permitted"
KVM: arm64: vhe: Drop extra isb() on guest exit
KVM: arm64: vhe: Synchronise with page table walker on MMU update
KVM: arm64: pkvm: Document the side effects of kvm_flush_dcache_to_poc()
KVM: arm64: nvhe: Synchronise with page table walker on TLBI
KVM: arm64: Handle 32bit CNTPCTSS traps
KVM: arm64: nvhe: Synchronise with page table walker on vcpu run
KVM: arm64: vgic: Don't acquire its_lock before config_lock
KVM: selftests: Add test to verify KVM's supported XCR0
...
117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* KVM L1 hypervisor optimizations on Hyper-V for SVM.
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*/
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#ifndef __ARCH_X86_KVM_SVM_ONHYPERV_H__
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#define __ARCH_X86_KVM_SVM_ONHYPERV_H__
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#include <asm/mshyperv.h>
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#if IS_ENABLED(CONFIG_HYPERV)
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#include "kvm_onhyperv.h"
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#include "svm/hyperv.h"
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static struct kvm_x86_ops svm_x86_ops;
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int svm_hv_enable_l2_tlb_flush(struct kvm_vcpu *vcpu);
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static inline bool svm_hv_is_enlightened_tlb_enabled(struct kvm_vcpu *vcpu)
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{
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struct hv_vmcb_enlightenments *hve = &to_svm(vcpu)->vmcb->control.hv_enlightenments;
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return ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB &&
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!!hve->hv_enlightenments_control.enlightened_npt_tlb;
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}
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static inline void svm_hv_init_vmcb(struct vmcb *vmcb)
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{
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struct hv_vmcb_enlightenments *hve = &vmcb->control.hv_enlightenments;
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BUILD_BUG_ON(sizeof(vmcb->control.hv_enlightenments) !=
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sizeof(vmcb->control.reserved_sw));
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if (npt_enabled &&
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ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB)
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hve->hv_enlightenments_control.enlightened_npt_tlb = 1;
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if (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)
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hve->hv_enlightenments_control.msr_bitmap = 1;
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}
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static inline __init void svm_hv_hardware_setup(void)
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{
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if (npt_enabled &&
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ms_hyperv.nested_features & HV_X64_NESTED_ENLIGHTENED_TLB) {
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pr_info(KBUILD_MODNAME ": Hyper-V enlightened NPT TLB flush enabled\n");
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svm_x86_ops.flush_remote_tlbs = hv_flush_remote_tlbs;
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svm_x86_ops.flush_remote_tlbs_range = hv_flush_remote_tlbs_range;
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}
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if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) {
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int cpu;
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pr_info(KBUILD_MODNAME ": Hyper-V Direct TLB Flush enabled\n");
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for_each_online_cpu(cpu) {
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struct hv_vp_assist_page *vp_ap =
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hv_get_vp_assist_page(cpu);
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if (!vp_ap)
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continue;
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vp_ap->nested_control.features.directhypercall = 1;
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}
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svm_x86_ops.enable_l2_tlb_flush =
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svm_hv_enable_l2_tlb_flush;
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}
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}
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static inline void svm_hv_vmcb_dirty_nested_enlightenments(
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struct kvm_vcpu *vcpu)
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{
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struct vmcb *vmcb = to_svm(vcpu)->vmcb;
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struct hv_vmcb_enlightenments *hve = &vmcb->control.hv_enlightenments;
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if (hve->hv_enlightenments_control.msr_bitmap)
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vmcb_mark_dirty(vmcb, HV_VMCB_NESTED_ENLIGHTENMENTS);
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}
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static inline void svm_hv_update_vp_id(struct vmcb *vmcb, struct kvm_vcpu *vcpu)
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{
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struct hv_vmcb_enlightenments *hve = &vmcb->control.hv_enlightenments;
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u32 vp_index = kvm_hv_get_vpindex(vcpu);
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if (hve->hv_vp_id != vp_index) {
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hve->hv_vp_id = vp_index;
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vmcb_mark_dirty(vmcb, HV_VMCB_NESTED_ENLIGHTENMENTS);
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}
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}
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#else
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static inline bool svm_hv_is_enlightened_tlb_enabled(struct kvm_vcpu *vcpu)
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{
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return false;
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}
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static inline void svm_hv_init_vmcb(struct vmcb *vmcb)
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{
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}
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static inline __init void svm_hv_hardware_setup(void)
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{
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}
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static inline void svm_hv_vmcb_dirty_nested_enlightenments(
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struct kvm_vcpu *vcpu)
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{
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}
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static inline void svm_hv_update_vp_id(struct vmcb *vmcb,
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struct kvm_vcpu *vcpu)
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{
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}
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#endif /* CONFIG_HYPERV */
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#endif /* __ARCH_X86_KVM_SVM_ONHYPERV_H__ */
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