20802d8d47
Inspired by commit 2e77a62cb3 ("arm64: extable: add a dedicated
uaccess handler"), do similar to riscv to add a dedicated uaccess
exception handler to update registers in exception context and
subsequently return back into the function which faulted, so we remove
the need for fixups specialized to each faulting instruction.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (c) 2018 Jim Wilson (jimw@sifive.com)
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*/
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#ifndef _ASM_RISCV_FUTEX_H
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#define _ASM_RISCV_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <linux/errno.h>
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#include <asm/asm.h>
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#include <asm/asm-extable.h>
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/* We don't even really need the extable code, but for now keep it simple */
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#ifndef CONFIG_MMU
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#define __enable_user_access() do { } while (0)
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#define __disable_user_access() do { } while (0)
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#endif
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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{ \
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__enable_user_access(); \
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__asm__ __volatile__ ( \
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"1: " insn " \n" \
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"2: \n" \
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_ASM_EXTABLE_UACCESS_ERR(1b, 2b, %[r]) \
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: [r] "+r" (ret), [ov] "=&r" (oldval), \
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[u] "+m" (*uaddr) \
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: [op] "Jr" (oparg) \
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: "memory"); \
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__disable_user_access(); \
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret = 0;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("amoswap.w.aqrl %[ov],%z[op],%[u]",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("amoadd.w.aqrl %[ov],%z[op],%[u]",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("amoor.w.aqrl %[ov],%z[op],%[u]",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("amoand.w.aqrl %[ov],%z[op],%[u]",
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ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("amoxor.w.aqrl %[ov],%z[op],%[u]",
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ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val;
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uintptr_t tmp;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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__enable_user_access();
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__asm__ __volatile__ (
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"1: lr.w.aqrl %[v],%[u] \n"
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" bne %[v],%z[ov],3f \n"
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"2: sc.w.aqrl %[t],%z[nv],%[u] \n"
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" bnez %[t],1b \n"
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"3: \n"
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_ASM_EXTABLE_UACCESS_ERR(1b, 3b, %[r]) \
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_ASM_EXTABLE_UACCESS_ERR(2b, 3b, %[r]) \
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: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
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: [ov] "Jr" (oldval), [nv] "Jr" (newval)
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: "memory");
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__disable_user_access();
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*uval = val;
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return ret;
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}
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#endif /* _ASM_RISCV_FUTEX_H */
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