e2c09648ab
Add bindings for DRAM MRQ GSC support. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
48 lines
1.2 KiB
YAML
48 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tegra CPU-NS - BPMP IPC reserved memory
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maintainers:
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- Peter De Schrijver <pdeschrijver@nvidia.com>
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description: |
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Define a memory region used for communication between CPU-NS and BPMP.
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Typically this node is created by the bootloader as the physical address
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has to be known to both CPU-NS and BPMP for correct IPC operation.
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The memory region is defined using a child node under /reserved-memory.
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The sub-node is named shmem@<address>.
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allOf:
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- $ref: reserved-memory.yaml
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properties:
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compatible:
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const: nvidia,tegra264-bpmp-shmem
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reg:
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description: The physical address and size of the shared SDRAM region
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- no-map
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examples:
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- |
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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dram_cpu_bpmp_mail: shmem@f1be0000 {
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compatible = "nvidia,tegra264-bpmp-shmem";
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reg = <0x0 0xf1be0000 0x0 0x2000>;
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no-map;
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};
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};
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...
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