76dedb9c0b
Document CPU clock management unit compatibles and add corresponding clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for the new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
354 lines
9.0 KiB
YAML
354 lines
9.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos850 SoC clock controller
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maintainers:
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- Sam Protsenko <semen.protsenko@linaro.org>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Exynos850 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. Root clocks in that clock tree are
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two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
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clocks must be defined as fixed-rate clocks in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'dt-bindings/clock/exynos850.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynos850-cmu-top
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- samsung,exynos850-cmu-apm
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- samsung,exynos850-cmu-aud
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-cpucl0
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- samsung,exynos850-cmu-cpucl1
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-g3d
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- samsung,exynos850-cmu-hsi
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- samsung,exynos850-cmu-is
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- samsung,exynos850-cmu-mfcmscl
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- samsung,exynos850-cmu-peri
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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clock-names:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-apm
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_APM bus clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_clkcmu_apm_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-aud
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: AUD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_aud
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cmgp
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_CMGP bus clock (from CMU_APM)
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clock-names:
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items:
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- const: oscclk
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- const: gout_clkcmu_cmgp_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-core
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_CORE bus clock (from CMU_TOP)
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- description: CCI clock (from CMU_TOP)
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- description: eMMC clock (from CMU_TOP)
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- description: SSS clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_core_bus
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- const: dout_core_cci
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- const: dout_core_mmc_embd
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- const: dout_core_sss
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cpucl0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CPUCL0 switch clock (from CMU_TOP)
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- description: CPUCL0 debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_cpucl0_switch
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- const: dout_cpucl0_dbg
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cpucl1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CPUCL1 switch clock (from CMU_TOP)
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- description: CPUCL1 debug clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_cpucl1_switch
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- const: dout_cpucl1_dbg
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-dpu
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: DPU clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_dpu
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-g3d
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: G3D clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_g3d_switch
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-hsi
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: External RTC clock (32768 Hz)
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- description: CMU_HSI bus clock (from CMU_TOP)
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- description: SD card clock (from CMU_TOP)
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- description: USB 2.0 DRD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: rtcclk
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- const: dout_hsi_bus
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- const: dout_hsi_mmc_card
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- const: dout_hsi_usb20drd
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-is
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_IS bus clock (from CMU_TOP)
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- description: Image Texture Processing core clock (from CMU_TOP)
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- description: Visual Recognition Accelerator clock (from CMU_TOP)
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- description: Geometric Distortion Correction clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_is_bus
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- const: dout_is_itp
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- const: dout_is_vra
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- const: dout_is_gdc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-mfcmscl
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: Multi-Format Codec clock (from CMU_TOP)
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- description: Memory to Memory Scaler clock (from CMU_TOP)
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- description: Multi-Channel Scaler clock (from CMU_TOP)
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- description: JPEG codec clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_mfcmscl_mfc
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- const: dout_mfcmscl_m2m
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- const: dout_mfcmscl_mcsc
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- const: dout_mfcmscl_jpeg
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-peri
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERI bus clock (from CMU_TOP)
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- description: UART clock (from CMU_TOP)
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- description: Parent clock for HSI2C and SPI (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_peri_bus
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- const: dout_peri_uart
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- const: dout_peri_ip
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERI
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- |
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#include <dt-bindings/clock/exynos850.h>
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cmu_peri: clock-controller@10030000 {
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compatible = "samsung,exynos850-cmu-peri";
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reg = <0x10030000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
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<&cmu_top CLK_DOUT_PERI_UART>,
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<&cmu_top CLK_DOUT_PERI_IP>;
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clock-names = "oscclk", "dout_peri_bus",
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"dout_peri_uart", "dout_peri_ip";
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};
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...
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