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linux/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
Niravkumar L Rabara d5f0942b50 dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2023-08-08 06:32:34 -05:00

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YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Agilex5 clock manager
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
The Intel Agilex5 Clock Manager is an integrated clock controller, which
generates and supplies clock to all the modules.
properties:
compatible:
const: intel,agilex5-clkmgr
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
#clock-cells = <1>;
};
...