d5f0942b50
Add clock ID definitions for Intel Agilex5 SoCFPGA. The registers in Agilex5 handling the clock is named as clock manager. Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
41 lines
798 B
YAML
41 lines
798 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel SoCFPGA Agilex5 clock manager
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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description:
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The Intel Agilex5 Clock Manager is an integrated clock controller, which
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generates and supplies clock to all the modules.
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properties:
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compatible:
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const: intel,agilex5-clkmgr
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clkmgr: clock-controller@10d10000 {
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compatible = "intel,agilex5-clkmgr";
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reg = <0x10d10000 0x1000>;
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#clock-cells = <1>;
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};
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...
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