9894949916
Add the S4 peripherals clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230904075504.23263-3-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
97 lines
2.4 KiB
YAML
97 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic S4 Peripherals Clock Controller
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maintainers:
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- Yu Tu <yu.tu@amlogic.com>
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properties:
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compatible:
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const: amlogic,s4-peripherals-clkc
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reg:
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maxItems: 1
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clocks:
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minItems: 14
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items:
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- description: input fixed pll div2
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- description: input fixed pll div2p5
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- description: input fixed pll div3
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- description: input fixed pll div4
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- description: input fixed pll div5
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input gp0 pll
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- description: input mpll0
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- description: input mpll1
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- description: input mpll2
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- description: input mpll3
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- description: input hdmi pll
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- description: input oscillator (usually at 24MHz)
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- description: input external 32kHz reference (optional)
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clock-names:
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minItems: 14
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items:
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- const: fclk_div2
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- const: fclk_div2p5
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- const: fclk_div3
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- const: fclk_div4
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- const: fclk_div5
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- const: fclk_div7
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- const: hifi_pll
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- const: gp0_pll
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- const: mpll0
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- const: mpll1
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- const: mpll2
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- const: mpll3
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- const: hdmi_pll
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- const: xtal
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- const: ext_32k
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
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clkc_periphs: clock-controller@fe000000 {
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compatible = "amlogic,s4-peripherals-clkc";
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reg = <0xfe000000 0x49c>;
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clocks = <&clkc_pll 3>,
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<&clkc_pll 13>,
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<&clkc_pll 5>,
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<&clkc_pll 7>,
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<&clkc_pll 9>,
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<&clkc_pll 11>,
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<&clkc_pll 17>,
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<&clkc_pll 15>,
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<&clkc_pll 25>,
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<&clkc_pll 27>,
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<&clkc_pll 29>,
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<&clkc_pll 31>,
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<&clkc_pll 20>,
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<&xtal>;
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clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
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"fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
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"mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
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#clock-cells = <1>;
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};
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...
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