4bedea9454
The attached patches provides part 2 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
67 lines
812 B
Plaintext
67 lines
812 B
Plaintext
OUTPUT_ARCH(xtensa)
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SECTIONS
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{
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.start 0xD0200000 : { *(.start) }
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.text :
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{
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__reloc_start = . ;
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_text_start = . ;
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*(.literal .text.literal .text)
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_text_end = . ;
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}
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.rodata ALIGN(0x04):
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{
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*(.rodata)
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*(.rodata1)
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}
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.data ALIGN(0x04):
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{
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*(.data)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.got.plt)
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*(.got)
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*(.dynamic)
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}
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__reloc_end = . ;
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.initrd ALIGN(0x10) :
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{
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boot_initrd_start = . ;
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*(.initrd)
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boot_initrd_end = .;
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}
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. = ALIGN(0x10);
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__image_load = . ;
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.image 0xd0001000: AT(__image_load)
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{
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_image_start = .;
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*(image)
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. = (. + 3) & ~ 3;
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_image_end = . ;
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}
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.bss ((LOADADDR(.image) + SIZEOF(.image) + 3) & ~ 3):
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{
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__bss_start = .;
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*(.sbss)
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*(.scommon)
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*(.dynbss)
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*(.bss)
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__bss_end = .;
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}
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_end = .;
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_param_start = .;
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PROVIDE (end = .);
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}
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