1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
185 lines
9.8 KiB
C
185 lines
9.8 KiB
C
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/*
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* File: include/asm-blackfin/mach-bf561/anomaly.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* This file shoule be up to date with:
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* - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1 or 0.4 silicon - sorry */
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#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
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#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
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#endif
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/* Issues that are common to 0.5 and 0.3 silicon */
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#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
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updated at the same time. */
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#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
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memory locations */
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#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
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registers */
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#define ANOMALY_05000127 /* Signbits instruction not functional under certain
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conditions */
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#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
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#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
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upper bits */
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#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
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#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
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syncs */
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#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
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and higher devices */
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#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
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#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
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#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
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functional */
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#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
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shadow of a conditional branch */
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#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
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may cause bad instruction fetches */
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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external SPORT TX and RX clocks */
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#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
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#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
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voltage regulator (VDDint) to increase */
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#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
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voltage regulator (VDDint) to decrease */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
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may be lost */
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#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
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#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
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registers are interrupted */
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#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
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#if (defined(CONFIG_BF_REV_0_5))
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#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
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mode with external clock */
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#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
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using IMDMA */
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#endif
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#if (defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
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Mode with 0 Frame Syncs */
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#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
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#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
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cache data writes */
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#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
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#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
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#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
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#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
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accumulator saturation */
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#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
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Purpose TX or RX modes */
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#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
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registers */
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#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
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External Frame Syncs */
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#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
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#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
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(not a meaningful mode) */
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#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
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Placement in Memory */
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#define ANOMALY_05000189 /* False Protection Exception */
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#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
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when polarity setting is changed */
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#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
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corruption */
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#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
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memory read */
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#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
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fix */
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#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
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inactive channels in certain conditions */
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#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
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situation */
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#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
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allocate cache lines on reads only mode */
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#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
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stopping */
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#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
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#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
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instructions */
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#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
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#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
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state */
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#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
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Non-Cached On-Chip L2 Memory */
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#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
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#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
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data */
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#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
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Differences in certain Conditions */
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#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
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#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
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multichannel mode */
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#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
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hardware reset */
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#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
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Control causes failures */
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#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
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#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
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(TDM) mode in certain conditions */
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#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
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reserved region */
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#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
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#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
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of the ICPLB Data registers differ */
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#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
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#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
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#define ANOMALY_05000262 /* Stores to data cache may be lost */
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#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
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exception */
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#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
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to last instruction in hardware loop */
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#define ANOMALY_05000276 /* Timing requirements change for External Frame
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Sync PPI Modes with non-zero PPI_DELAY */
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#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
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DMA system instability */
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
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in a particular stage */
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#define ANOMALY_05000287 /* A read will receive incorrect data under certain
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conditions */
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#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
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#endif
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#endif /* _MACH_ANOMALY_H_ */
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