e003934876
And stick the iommu archdata pointer into the generic OF device tree of_device struct as well. We still have to pass the sbus_bus object down into the routines so that the SBUS bus objects get the iommu cookies set properly. After drivers get converted to being pure OF drivers, that can go away. Signed-off-by: David S. Miller <davem@davemloft.net>
124 lines
5.7 KiB
C
124 lines
5.7 KiB
C
/* iommu.h: Definitions for the sun4m IOMMU.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_IOMMU_H
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#define _SPARC_IOMMU_H
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#include <asm/page.h>
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#include <asm/bitext.h>
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/* The iommu handles all virtual to physical address translations
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* that occur between the SBUS and physical memory. Access by
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* the cpu to IO registers and similar go over the mbus so are
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* translated by the on chip SRMMU. The iommu and the srmmu do
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* not need to have the same translations at all, in fact most
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* of the time the translations they handle are a disjunct set.
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* Basically the iommu handles all dvma sbus activity.
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*/
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/* The IOMMU registers occupy three pages in IO space. */
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struct iommu_regs {
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/* First page */
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volatile unsigned long control; /* IOMMU control */
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volatile unsigned long base; /* Physical base of iopte page table */
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volatile unsigned long _unused1[3];
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volatile unsigned long tlbflush; /* write only */
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volatile unsigned long pageflush; /* write only */
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volatile unsigned long _unused2[1017];
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/* Second page */
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volatile unsigned long afsr; /* Async-fault status register */
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volatile unsigned long afar; /* Async-fault physical address */
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volatile unsigned long _unused3[2];
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volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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volatile unsigned long sbuscfg1;
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volatile unsigned long sbuscfg2;
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volatile unsigned long sbuscfg3;
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volatile unsigned long mfsr; /* Memory-fault status register */
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volatile unsigned long mfar; /* Memory-fault physical address */
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volatile unsigned long _unused4[1014];
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/* Third page */
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volatile unsigned long mid; /* IOMMU module-id */
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};
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#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
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#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
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#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
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#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
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#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
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#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
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#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
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#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
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#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
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#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
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#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
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#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
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#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
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#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
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#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
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produced by this device as pure
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physical. */
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#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
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#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
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#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
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#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
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on the even word of the access, low bit
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indicated odd word caused the parity error */
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#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
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#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
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#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
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#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
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#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
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#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
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#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
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#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
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#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
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#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
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/* The format of an iopte in the page tables */
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#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
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#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
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#define IOPTE_WRITE 0x00000004 /* Writeable */
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#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
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#define IOPTE_WAZ 0x00000001 /* Write as zeros */
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struct iommu_struct {
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struct iommu_regs *regs;
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iopte_t *page_table;
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/* For convenience */
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unsigned long start; /* First managed virtual address */
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unsigned long end; /* Last managed virtual address */
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struct bit_map usemap;
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};
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static inline void iommu_invalidate(struct iommu_regs *regs)
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{
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regs->tlbflush = 0;
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}
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static inline void iommu_invalidate_page(struct iommu_regs *regs, unsigned long ba)
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{
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regs->pageflush = (ba & PAGE_MASK);
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}
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extern void iommu_init(struct device_node *dp, struct sbus_bus *sbus);
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#endif /* !(_SPARC_IOMMU_H) */
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