c1738904d6
Reverted the 'Fix unintended auto configurations in cx18-av-core' patch, instead disable the auto config completely. Fix a bug in cx18_av_vbi_setup() where the standard tests were done in the wrong order. Tested with NTSC-M, PAL-BG, PAL-I, PAL-DK, PAL-M, PAL-Nc, SECAM-DK, SECAM-L and SECAM-BG. The last one does not work at the moment due to a tda9887.c bug. Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
409 lines
10 KiB
C
409 lines
10 KiB
C
/*
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* cx18 ADEC VBI functions
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*
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* Derived from cx25840-vbi.c
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include "cx18-driver.h"
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static int odd_parity(u8 c)
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{
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c ^= (c >> 4);
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c ^= (c >> 2);
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c ^= (c >> 1);
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return c & 1;
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}
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static int decode_vps(u8 *dst, u8 *p)
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{
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static const u8 biphase_tbl[] = {
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0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
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0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
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0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
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0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
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0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
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0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
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0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
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0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
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0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
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0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
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0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
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0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
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0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
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0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
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0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
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0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
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0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
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0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
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0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
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0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
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0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
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0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
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0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
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0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
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0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
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0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
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0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
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0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
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0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
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0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
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0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
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0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
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};
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u8 c, err = 0;
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int i;
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for (i = 0; i < 2 * 13; i += 2) {
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err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
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c = (biphase_tbl[p[i + 1]] & 0xf) |
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((biphase_tbl[p[i]] & 0xf) << 4);
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dst[i / 2] = c;
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}
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return err & 0xf0;
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}
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void cx18_av_vbi_setup(struct cx18 *cx)
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{
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struct cx18_av_state *state = &cx->av_state;
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v4l2_std_id std = state->std;
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int hblank, hactive, burst, vblank, vactive, sc;
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int vblank656, src_decimation;
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int luma_lpf, uv_lpf, comb;
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u32 pll_int, pll_frac, pll_post;
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/* datasheet startup, step 8d */
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if (std & ~V4L2_STD_NTSC)
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cx18_av_write(cx, 0x49f, 0x11);
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else
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cx18_av_write(cx, 0x49f, 0x14);
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if (std & V4L2_STD_625_50) {
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hblank = 0x084;
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hactive = 0x2d0;
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burst = 0x5d;
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vblank = 0x024;
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vactive = 0x244;
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vblank656 = 0x28;
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src_decimation = 0x21f;
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luma_lpf = 2;
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if (std & V4L2_STD_PAL) {
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uv_lpf = 1;
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comb = 0x20;
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sc = 0x0a8263;
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} else if (std == V4L2_STD_PAL_Nc) {
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uv_lpf = 1;
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comb = 0x20;
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sc = 0x087da5;
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} else { /* SECAM */
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uv_lpf = 0;
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comb = 0;
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sc = 0x0a425f;
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}
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} else {
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hactive = 720;
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hblank = 122;
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vactive = 487;
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luma_lpf = 1;
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uv_lpf = 1;
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vblank = 26;
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vblank656 = 26;
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src_decimation = 0x21f;
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if (std == V4L2_STD_PAL_60) {
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burst = 0x5b;
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luma_lpf = 2;
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comb = 0x20;
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sc = 0x0a8263;
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} else if (std == V4L2_STD_PAL_M) {
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burst = 0x61;
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comb = 0x20;
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sc = 555452;
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} else {
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burst = 0x5b;
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comb = 0x66;
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sc = 556063;
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}
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}
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/* DEBUG: Displays configured PLL frequency */
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pll_int = cx18_av_read(cx, 0x108);
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pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff;
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pll_post = cx18_av_read(cx, 0x109);
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CX18_DEBUG_INFO("PLL regs = int: %u, frac: %u, post: %u\n",
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pll_int, pll_frac, pll_post);
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if (pll_post) {
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int fin, fsc;
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int pll = 28636363L * ((((u64)pll_int) << 25) + pll_frac);
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pll >>= 25;
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pll /= pll_post;
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CX18_DEBUG_INFO("PLL = %d.%06d MHz\n",
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pll / 1000000, pll % 1000000);
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CX18_DEBUG_INFO("PLL/8 = %d.%06d MHz\n",
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pll / 8000000, (pll / 8) % 1000000);
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fin = ((u64)src_decimation * pll) >> 12;
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CX18_DEBUG_INFO("ADC Sampling freq = %d.%06d MHz\n",
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fin / 1000000, fin % 1000000);
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fsc = (((u64)sc) * pll) >> 24L;
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CX18_DEBUG_INFO("Chroma sub-carrier freq = %d.%06d MHz\n",
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fsc / 1000000, fsc % 1000000);
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CX18_DEBUG_INFO("hblank %i, hactive %i, "
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"vblank %i , vactive %i, vblank656 %i, src_dec %i,"
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"burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x,"
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" sc 0x%06x\n",
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hblank, hactive, vblank, vactive, vblank656,
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src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
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}
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/* Sets horizontal blanking delay and active lines */
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cx18_av_write(cx, 0x470, hblank);
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cx18_av_write(cx, 0x471, 0xff & (((hblank >> 8) & 0x3) |
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(hactive << 4)));
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cx18_av_write(cx, 0x472, hactive >> 4);
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/* Sets burst gate delay */
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cx18_av_write(cx, 0x473, burst);
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/* Sets vertical blanking delay and active duration */
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cx18_av_write(cx, 0x474, vblank);
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cx18_av_write(cx, 0x475, 0xff & (((vblank >> 8) & 0x3) |
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(vactive << 4)));
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cx18_av_write(cx, 0x476, vactive >> 4);
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cx18_av_write(cx, 0x477, vblank656);
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/* Sets src decimation rate */
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cx18_av_write(cx, 0x478, 0xff & src_decimation);
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cx18_av_write(cx, 0x479, 0xff & (src_decimation >> 8));
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/* Sets Luma and UV Low pass filters */
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cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
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/* Enables comb filters */
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cx18_av_write(cx, 0x47b, comb);
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/* Sets SC Step*/
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cx18_av_write(cx, 0x47c, sc);
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cx18_av_write(cx, 0x47d, 0xff & sc >> 8);
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cx18_av_write(cx, 0x47e, 0xff & sc >> 16);
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/* Sets VBI parameters */
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if (std & V4L2_STD_625_50) {
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cx18_av_write(cx, 0x47f, 0x01);
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state->vbi_line_offset = 5;
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} else {
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cx18_av_write(cx, 0x47f, 0x00);
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state->vbi_line_offset = 8;
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}
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}
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int cx18_av_vbi(struct cx18 *cx, unsigned int cmd, void *arg)
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{
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struct cx18_av_state *state = &cx->av_state;
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struct v4l2_format *fmt;
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struct v4l2_sliced_vbi_format *svbi;
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switch (cmd) {
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case VIDIOC_G_FMT:
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{
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static u16 lcr2vbi[] = {
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0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
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0, V4L2_SLICED_WSS_625, 0, /* 4 */
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V4L2_SLICED_CAPTION_525, /* 6 */
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0, 0, V4L2_SLICED_VPS, 0, 0, /* 9 */
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0, 0, 0, 0
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};
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int is_pal = !(state->std & V4L2_STD_525_60);
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int i;
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fmt = arg;
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if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
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return -EINVAL;
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svbi = &fmt->fmt.sliced;
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memset(svbi, 0, sizeof(*svbi));
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/* we're done if raw VBI is active */
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if ((cx18_av_read(cx, 0x404) & 0x10) == 0)
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break;
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if (is_pal) {
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for (i = 7; i <= 23; i++) {
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u8 v = cx18_av_read(cx, 0x424 + i - 7);
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svbi->service_lines[0][i] = lcr2vbi[v >> 4];
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svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
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svbi->service_set |= svbi->service_lines[0][i] |
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svbi->service_lines[1][i];
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}
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} else {
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for (i = 10; i <= 21; i++) {
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u8 v = cx18_av_read(cx, 0x424 + i - 10);
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svbi->service_lines[0][i] = lcr2vbi[v >> 4];
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svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
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svbi->service_set |= svbi->service_lines[0][i] |
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svbi->service_lines[1][i];
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}
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}
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break;
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}
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case VIDIOC_S_FMT:
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{
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int is_pal = !(state->std & V4L2_STD_525_60);
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int vbi_offset = is_pal ? 1 : 0;
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int i, x;
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u8 lcr[24];
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fmt = arg;
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if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
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return -EINVAL;
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svbi = &fmt->fmt.sliced;
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if (svbi->service_set == 0) {
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/* raw VBI */
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memset(svbi, 0, sizeof(*svbi));
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/* Setup VBI */
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cx18_av_vbi_setup(cx);
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/* VBI Offset */
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cx18_av_write(cx, 0x47f, vbi_offset);
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cx18_av_write(cx, 0x404, 0x2e);
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break;
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}
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for (x = 0; x <= 23; x++)
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lcr[x] = 0x00;
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/* Setup VBI */
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cx18_av_vbi_setup(cx);
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/* Sliced VBI */
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cx18_av_write(cx, 0x404, 0x32); /* Ancillary data */
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cx18_av_write(cx, 0x406, 0x13);
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cx18_av_write(cx, 0x47f, vbi_offset);
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if (is_pal) {
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for (i = 0; i <= 6; i++)
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svbi->service_lines[0][i] =
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svbi->service_lines[1][i] = 0;
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} else {
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for (i = 0; i <= 9; i++)
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svbi->service_lines[0][i] =
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svbi->service_lines[1][i] = 0;
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for (i = 22; i <= 23; i++)
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svbi->service_lines[0][i] =
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svbi->service_lines[1][i] = 0;
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}
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for (i = 7; i <= 23; i++) {
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for (x = 0; x <= 1; x++) {
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switch (svbi->service_lines[1-x][i]) {
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case V4L2_SLICED_TELETEXT_B:
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lcr[i] |= 1 << (4 * x);
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break;
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case V4L2_SLICED_WSS_625:
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lcr[i] |= 4 << (4 * x);
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break;
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case V4L2_SLICED_CAPTION_525:
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lcr[i] |= 6 << (4 * x);
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break;
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case V4L2_SLICED_VPS:
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lcr[i] |= 9 << (4 * x);
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break;
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}
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}
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}
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if (is_pal) {
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for (x = 1, i = 0x424; i <= 0x434; i++, x++)
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cx18_av_write(cx, i, lcr[6 + x]);
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} else {
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for (x = 1, i = 0x424; i <= 0x430; i++, x++)
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cx18_av_write(cx, i, lcr[9 + x]);
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for (i = 0x431; i <= 0x434; i++)
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cx18_av_write(cx, i, 0);
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}
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cx18_av_write(cx, 0x43c, 0x16);
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cx18_av_write(cx, 0x474, is_pal ? 0x2a : 0x22);
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break;
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}
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case VIDIOC_INT_DECODE_VBI_LINE:
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{
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struct v4l2_decode_vbi_line *vbi = arg;
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u8 *p = vbi->p;
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int id1, id2, l, err = 0;
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if (p[0] || p[1] != 0xff || p[2] != 0xff ||
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(p[3] != 0x55 && p[3] != 0x91)) {
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vbi->line = vbi->type = 0;
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break;
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}
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p += 4;
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id1 = p[-1];
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id2 = p[0] & 0xf;
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l = p[2] & 0x3f;
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l += state->vbi_line_offset;
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p += 4;
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switch (id2) {
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case 1:
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id2 = V4L2_SLICED_TELETEXT_B;
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break;
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case 4:
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id2 = V4L2_SLICED_WSS_625;
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break;
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case 6:
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id2 = V4L2_SLICED_CAPTION_525;
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err = !odd_parity(p[0]) || !odd_parity(p[1]);
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break;
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case 9:
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id2 = V4L2_SLICED_VPS;
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if (decode_vps(p, p) != 0)
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err = 1;
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break;
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default:
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id2 = 0;
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err = 1;
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break;
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}
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vbi->type = err ? 0 : id2;
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vbi->line = err ? 0 : l;
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vbi->is_second_field = err ? 0 : (id1 == 0x55);
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vbi->p = p;
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break;
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}
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}
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return 0;
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}
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