Oskar Schirmer a81cbd2da4 xtensa: enforce slab alignment to maximum register width ... XCHAL_DATA_WIDTH is the maximum register width, slab caches should be aligned to this. Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4 (wordsize) for now. But the S6000 variant will raise this to 16. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>		2009-04-02 23:41:16 -07:00
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asmmacro.h
atomic.h
auxvec.h
bitops.h
bootparam.h
bug.h
bugs.h
byteorder.h	byteorder: make swab.h include asm/swab.h like a regular header	2009-01-14 19:56:50 -08:00
cache.h
cacheasm.h
cacheflush.h
checksum.h
coprocessor.h
cpumask.h
cputime.h
current.h
delay.h
device.h
div64.h
dma-mapping.h
dma.h
elf.h
emergency-restart.h
errno.h
fb.h
fcntl.h
futex.h
hardirq.h
highmem.h
hw_irq.h
io.h
ioctl.h
ioctls.h
ipcbuf.h
irq_regs.h
irq.h
Kbuild	byteorder: make swab.h include asm/swab.h like a regular header	2009-01-14 19:56:50 -08:00
kdebug.h
kmap_types.h
linkage.h
local.h
mman.h
mmu_context.h	xtensa: remove redefinition of XCHAL_MMU_ASID_BITS	2009-04-02 23:38:10 -07:00
mmu.h
module.h
msgbuf.h
mutex.h
page.h	xtensa: cope with ram beginning at higher addresses	2009-04-02 23:41:08 -07:00
param.h
pci-bridge.h
pci.h
percpu.h
pgalloc.h
pgtable.h
platform.h
poll.h
posix_types.h
processor.h	xtensa: enforce slab alignment to maximum register width	2009-04-02 23:41:16 -07:00
ptrace.h
regs.h
resource.h
rmap.h
rwsem.h
scatterlist.h
sections.h
segment.h
sembuf.h
serial.h
setup.h
shmbuf.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
smp.h
socket.h	net: new user space API for time stamping of incoming and outgoing packets	2009-02-15 22:43:33 -08:00
sockios.h
spinlock.h
stat.h
statfs.h
string.h
swab.h	headers_check fix: xtensa, swab.h	2009-02-01 11:01:30 +05:30
syscall.h
system.h
termbits.h
termios.h
thread_info.h
timex.h
tlb.h
tlbflush.h
topology.h
types.h
uaccess.h
ucontext.h
unaligned.h
unistd.h
user.h
vga.h
xor.h