1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
631 lines
18 KiB
C
631 lines
18 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf GmbH
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* Copyright (C) 1994 - 2000 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/processor.h>
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#include <mangle-port.h>
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* Raw operations are never swapped in software. Otoh values that raw
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* operations are working on may or may not have been swapped by the bus
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* hardware. An example use would be for flash memory that's used for
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* execute in place.
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*/
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# define __raw_ioswabb(x) (x)
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# define __raw_ioswabw(x) (x)
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# define __raw_ioswabl(x) (x)
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# define __raw_ioswabq(x) (x)
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/*
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* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
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* less sane hardware forces software to fiddle with this...
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*/
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#if defined(CONFIG_SWAP_IO_SPACE)
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# define ioswabb(x) (x)
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# ifdef CONFIG_SGI_IP22
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/*
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* IP22 seems braindead enough to swap 16bits values in hardware, but
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* not 32bits. Go figure... Can't tell without documentation.
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*/
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# define ioswabw(x) (x)
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# else
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# define ioswabw(x) le16_to_cpu(x)
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# endif
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# define ioswabl(x) le32_to_cpu(x)
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# define ioswabq(x) le64_to_cpu(x)
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#else
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# define ioswabb(x) (x)
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# define ioswabw(x) (x)
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# define ioswabl(x) (x)
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# define ioswabq(x) (x)
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#endif
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/*
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* Native bus accesses never swapped.
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*/
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#define bus_ioswabb(x) (x)
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#define bus_ioswabw(x) (x)
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#define bus_ioswabl(x) (x)
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#define bus_ioswabq(x) (x)
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#define __bus_ioswabq bus_ioswabq
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#define IO_SPACE_LIMIT 0xffff
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/*
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* On MIPS I/O ports are memory mapped, so we access them using normal
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* load/store instructions. mips_io_port_base is the virtual address to
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* which all ports are being mapped. For sake of efficiency some code
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* assumes that this is an address that can be loaded with a single lui
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* instruction, so the lower 16 bits must be zero. Should be true on
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* on any sane architecture; generic code does not use this assumption.
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*/
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extern const unsigned long mips_io_port_base;
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#define set_io_port_base(base) \
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do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*
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*/
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#define __SLOW_DOWN_IO \
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__asm__ __volatile__( \
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"sb\t$0,0x80(%0)" \
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: : "r" (mips_io_port_base));
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#ifdef CONF_SLOWDOWN_IO
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#ifdef REALLY_SLOW_IO
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#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
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#else
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#define SLOW_DOWN_IO __SLOW_DOWN_IO
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#endif
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#else
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#define SLOW_DOWN_IO
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#endif
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/*
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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*
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* The returned physical address is the physical (CPU) mapping for
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* the memory address given. It is only valid to use this function on
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* addresses directly mapped or allocated via kmalloc.
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*
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* This function does not give bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline unsigned long virt_to_phys(volatile void * address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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/*
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* phys_to_virt - map physical address to virtual
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* @address: address to remap
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*
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* The returned virtual address is a current CPU mapping for
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* the memory address given. It is only valid to use this function on
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* addresses that have a kernel mapping
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*
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* This function does not handle bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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*/
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static inline unsigned long isa_virt_to_bus(volatile void * address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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static inline void * isa_bus_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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#define isa_page_to_bus page_to_phys
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/*
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* However PCI ones are not necessarily 1:1 and therefore these interfaces
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* are forbidden in portable PCI drivers.
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*
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* Allow them for x86 for legacy drivers, though.
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
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* for the processor. This implies the assumption that there is only
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* one of these busses.
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*/
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extern unsigned long isa_slot_offset;
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
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extern void __iounmap(volatile void __iomem *addr);
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static inline void * __ioremap_mode(phys_t offset, unsigned long size,
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unsigned long flags)
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{
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if (cpu_has_64bit_addresses) {
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u64 base = UNCAC_BASE;
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/*
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* R10000 supports a 2 bit uncached attribute therefore
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* UNCAC_BASE may not equal IO_BASE.
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*/
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if (flags == _CACHE_UNCACHED)
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base = (u64) IO_BASE;
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return (void *) (unsigned long) (base + offset);
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}
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return __ioremap(offset, size, flags);
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}
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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/*
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* ioremap_nocache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* on the CPU as well as honouring existing caching rules from things like
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* the PCI bus. Note that there are other caches and buffers on many
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* busses. In paticular driver authors should read up on PCI writes
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*
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* It's useful if some control registers are in such an area and
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* write combining or read caching is not desirable:
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*/
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#define ioremap_nocache(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED)
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/*
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* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
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* requests a cachable mapping, ioremap_uncached_accelerated requests a
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* mapping using the uncached accelerated mode which isn't supported on
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* all processors.
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*/
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#define ioremap_cacheable_cow(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
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#define ioremap_uncached_accelerated(offset, size) \
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__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
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static inline void iounmap(volatile void __iomem *addr)
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{
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if (cpu_has_64bit_addresses)
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return;
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__iounmap(addr);
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}
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
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\
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static inline void pfx##write##bwlq(type val, \
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volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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__val = pfx##ioswab##bwlq(val); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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*__mem = __val; \
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else if (cpu_has_64bits) { \
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unsigned long __flags; \
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type __tmp; \
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\
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if (irq) \
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set mips3" "\t\t# __writeq""\n\t" \
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"dsll32 %L0, %L0, 0" "\n\t" \
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"dsrl32 %L0, %L0, 0" "\n\t" \
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"dsll32 %M0, %M0, 0" "\n\t" \
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"or %L0, %L0, %M0" "\n\t" \
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"sd %L0, %2" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__tmp) \
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: "0" (__val), "m" (*__mem)); \
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if (irq) \
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local_irq_restore(__flags); \
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} else \
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BUG(); \
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} \
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\
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static inline type pfx##read##bwlq(volatile void __iomem *mem) \
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{ \
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volatile type *__mem; \
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type __val; \
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\
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__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
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\
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if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
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__val = *__mem; \
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else if (cpu_has_64bits) { \
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unsigned long __flags; \
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\
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set mips3" "\t\t# __readq" "\n\t" \
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"ld %L0, %1" "\n\t" \
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"dsra32 %M0, %L0, 0" "\n\t" \
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"sll %L0, %L0, 0" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__val) \
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: "m" (*__mem)); \
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local_irq_restore(__flags); \
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} else { \
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__val = 0; \
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BUG(); \
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} \
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\
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return pfx##ioswab##bwlq(__val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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port = __swizzle_addr_##bwlq(port); \
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__addr = (void *)(mips_io_port_base + port); \
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\
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__val = pfx##ioswab##bwlq(val); \
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\
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if (sizeof(type) != sizeof(u64)) { \
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*__addr = __val; \
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slow; \
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} else \
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BUILD_BUG(); \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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port = __swizzle_addr_##bwlq(port); \
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__addr = (void *)(mips_io_port_base + port); \
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\
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if (sizeof(type) != sizeof(u64)) { \
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__val = *__addr; \
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slow; \
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} else { \
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__val = 0; \
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BUILD_BUG(); \
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} \
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\
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return pfx##ioswab##bwlq(__val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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\
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
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#define BUILDIO(bwlq, type) \
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\
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__BUILD_MEMORY_PFX(, bwlq, type) \
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__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
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__BUILD_MEMORY_PFX(bus_, bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type) \
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__BUILD_IOPORT_PFX(__raw_, bwlq, type)
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#define __BUILDIO(bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
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BUILDIO(b, u8)
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BUILDIO(w, u16)
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BUILDIO(l, u32)
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BUILDIO(q, u64)
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__BUILDIO(q, u64)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readq_relaxed readq
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/*
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* Some code tests for these symbols
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*/
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#define readq readq
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#define writeq writeq
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#define __BUILD_MEMORY_STRING(bwlq, type) \
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\
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static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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|
|
|
#define __BUILD_IOPORT_STRING(bwlq, type) \
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\
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static inline void outs##bwlq(unsigned long port, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_out##bwlq(*__addr, port); \
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__addr++; \
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} \
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} \
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\
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static inline void ins##bwlq(unsigned long port, void *addr, \
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|
unsigned int count) \
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|
{ \
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|
volatile type *__addr = addr; \
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|
\
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|
while (count--) { \
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|
*__addr = __raw_in##bwlq(port); \
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__addr++; \
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} \
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|
}
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|
|
|
#define BUILDSTRING(bwlq, type) \
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|
\
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|
__BUILD_MEMORY_STRING(bwlq, type) \
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|
__BUILD_IOPORT_STRING(bwlq, type)
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|
|
|
BUILDSTRING(b, u8)
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BUILDSTRING(w, u16)
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BUILDSTRING(l, u32)
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BUILDSTRING(q, u64)
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|
|
|
|
|
/* Depends on MIPS II instruction set */
|
|
#define mmiowb() asm volatile ("sync" ::: "memory")
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|
|
|
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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|
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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|
|
|
/*
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* Memory Mapped I/O
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|
*/
|
|
#define ioread8(addr) readb(addr)
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|
#define ioread16(addr) readw(addr)
|
|
#define ioread32(addr) readl(addr)
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|
|
|
#define iowrite8(b,addr) writeb(b,addr)
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|
#define iowrite16(w,addr) writew(w,addr)
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|
#define iowrite32(l,addr) writel(l,addr)
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#define ioread8_rep(a,b,c) readsb(a,b,c)
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#define ioread16_rep(a,b,c) readsw(a,b,c)
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#define ioread32_rep(a,b,c) readsl(a,b,c)
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|
|
#define iowrite8_rep(a,b,c) writesb(a,b,c)
|
|
#define iowrite16_rep(a,b,c) writesw(a,b,c)
|
|
#define iowrite32_rep(a,b,c) writesl(a,b,c)
|
|
|
|
/* Create a virtual mapping cookie for an IO port range */
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
|
|
extern void ioport_unmap(void __iomem *);
|
|
|
|
/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
|
|
struct pci_dev;
|
|
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
|
|
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
|
|
|
|
/*
|
|
* ISA space is 'always mapped' on currently supported MIPS systems, no need
|
|
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
|
|
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
|
|
* are physical addresses. The following constant pointer can be
|
|
* used as the IO-area pointer (it can be iounmapped as well, so the
|
|
* analogy with PCI is quite large):
|
|
*/
|
|
#define __ISA_IO_base ((char *)(isa_slot_offset))
|
|
|
|
#define isa_readb(a) readb(__ISA_IO_base + (a))
|
|
#define isa_readw(a) readw(__ISA_IO_base + (a))
|
|
#define isa_readl(a) readl(__ISA_IO_base + (a))
|
|
#define isa_readq(a) readq(__ISA_IO_base + (a))
|
|
#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
|
|
#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
|
|
#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
|
|
#define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
|
|
#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
|
|
#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
|
|
#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
|
|
|
|
/*
|
|
* We don't have csum_partial_copy_fromio() yet, so we cheat here and
|
|
* just copy it. The net code will then do the checksum later.
|
|
*/
|
|
#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
|
|
#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
|
|
|
|
/*
|
|
* check_signature - find BIOS signatures
|
|
* @io_addr: mmio address to check
|
|
* @signature: signature block
|
|
* @length: length of signature
|
|
*
|
|
* Perform a signature comparison with the mmio address io_addr. This
|
|
* address should have been obtained by ioremap.
|
|
* Returns 1 on a match.
|
|
*/
|
|
static inline int check_signature(char __iomem *io_addr,
|
|
const unsigned char *signature, int length)
|
|
{
|
|
int retval = 0;
|
|
do {
|
|
if (readb(io_addr) != *signature)
|
|
goto out;
|
|
io_addr++;
|
|
signature++;
|
|
length--;
|
|
} while (length);
|
|
retval = 1;
|
|
out:
|
|
return retval;
|
|
}
|
|
|
|
/*
|
|
* The caches on some architectures aren't dma-coherent and have need to
|
|
* handle this in software. There are three types of operations that
|
|
* can be applied to dma buffers.
|
|
*
|
|
* - dma_cache_wback_inv(start, size) makes caches and coherent by
|
|
* writing the content of the caches back to memory, if necessary.
|
|
* The function also invalidates the affected part of the caches as
|
|
* necessary before DMA transfers from outside to memory.
|
|
* - dma_cache_wback(start, size) makes caches and coherent by
|
|
* writing the content of the caches back to memory, if necessary.
|
|
* The function also invalidates the affected part of the caches as
|
|
* necessary before DMA transfers from outside to memory.
|
|
* - dma_cache_inv(start, size) invalidates the affected parts of the
|
|
* caches. Dirty lines of the caches may be written back or simply
|
|
* be discarded. This operation is necessary before dma operations
|
|
* to the memory.
|
|
*/
|
|
#ifdef CONFIG_DMA_NONCOHERENT
|
|
|
|
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
|
|
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
|
|
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
|
|
|
|
#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
|
|
#define dma_cache_wback(start, size) _dma_cache_wback(start,size)
|
|
#define dma_cache_inv(start, size) _dma_cache_inv(start,size)
|
|
|
|
#else /* Sane hardware */
|
|
|
|
#define dma_cache_wback_inv(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
#define dma_cache_wback(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
#define dma_cache_inv(start,size) \
|
|
do { (void) (start); (void) (size); } while (0)
|
|
|
|
#endif /* CONFIG_DMA_NONCOHERENT */
|
|
|
|
/*
|
|
* Read a 32-bit register that requires a 64-bit read cycle on the bus.
|
|
* Avoid interrupt mucking, just adjust the address for 4-byte access.
|
|
* Assume the addresses are 8-byte aligned.
|
|
*/
|
|
#ifdef __MIPSEB__
|
|
#define __CSR_32_ADJUST 4
|
|
#else
|
|
#define __CSR_32_ADJUST 0
|
|
#endif
|
|
|
|
#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
|
|
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
#endif /* _ASM_IO_H */
|