6b783f7c5d
irq_domain_add_simple() was a stop-gap measure until complete irq_domain support was complete. This patch removes the irq_domain_add_simple() interface. This patch also drops the explicit irq_domain initialization performed by the mach-versatile code because the versatile interrupt controller already has irq_domain support built into it. This was a bug that was hanging around quietly for a while, but with the full irq_domain which actually verifies that irq_domain ranges are available it would cause the registration to fail and the system wouldn't boot. v4: Fixed number of irqs in mx5 gpio code v2: Updated to pass in host_data pointer on irq_domain allocation. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Milton Miller <miltonm@bga.com> Cc: Russell King <linux@arm.linux.org.uk> Tested-by: Olof Johansson <olof@lixom.net>
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* interrupt controller support for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqdomain.h>
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#include <linux/syscore_ops.h>
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#define SIRFSOC_INT_RISC_MASK0 0x0018
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#define SIRFSOC_INT_RISC_MASK1 0x001C
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#define SIRFSOC_INT_RISC_LEVEL0 0x0020
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#define SIRFSOC_INT_RISC_LEVEL1 0x0024
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void __iomem *sirfsoc_intc_base;
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static __init void
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sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
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}
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static __init void sirfsoc_irq_init(void)
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{
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sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
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sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
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}
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static struct of_device_id intc_ids[] = {
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{ .compatible = "sirf,prima2-intc" },
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{},
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};
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void __init sirfsoc_of_irq_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, intc_ids);
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if (!np)
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panic("unable to find compatible intc node in dtb\n");
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sirfsoc_intc_base = of_iomap(np, 0);
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if (!sirfsoc_intc_base)
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panic("unable to map intc cpu registers\n");
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irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL);
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of_node_put(np);
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sirfsoc_irq_init();
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}
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struct sirfsoc_irq_status {
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u32 mask0;
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u32 mask1;
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u32 level0;
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u32 level1;
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};
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static struct sirfsoc_irq_status sirfsoc_irq_st;
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static int sirfsoc_irq_suspend(void)
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{
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sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
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sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
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sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
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sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
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return 0;
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}
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static void sirfsoc_irq_resume(void)
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{
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writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
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writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
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}
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static struct syscore_ops sirfsoc_irq_syscore_ops = {
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.suspend = sirfsoc_irq_suspend,
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.resume = sirfsoc_irq_resume,
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};
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static int __init sirfsoc_irq_pm_init(void)
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{
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register_syscore_ops(&sirfsoc_irq_syscore_ops);
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return 0;
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}
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device_initcall(sirfsoc_irq_pm_init);
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