a0c9a822bf
Intel spec says that TMR needs to be set/cleared when IRR is set, but kvm also clears it on EOI. I did some tests on a real (AMD based) system, and I see same TMR values both before and after EOI, so I think it's a minor bug in kvm. This patch fixes TMR to be set/cleared on IRR set only as per spec. And now that we don't clear TMR, we can save an atomic read of TMR on EOI that's not propagated to ioapic, by checking whether ioapic needs a specific vector first and calculating the mode afterwards. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
#ifndef __KVM_IO_APIC_H
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#define __KVM_IO_APIC_H
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#include <linux/kvm_host.h>
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#include "iodev.h"
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struct kvm;
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struct kvm_vcpu;
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#define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
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#define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
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#define IOAPIC_EDGE_TRIG 0
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#define IOAPIC_LEVEL_TRIG 1
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#define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
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#define IOAPIC_MEM_LENGTH 0x100
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/* Direct registers. */
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#define IOAPIC_REG_SELECT 0x00
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#define IOAPIC_REG_WINDOW 0x10
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#define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
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/* Indirect registers. */
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#define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
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#define IOAPIC_REG_VERSION 0x01
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#define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
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/*ioapic delivery mode*/
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#define IOAPIC_FIXED 0x0
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#define IOAPIC_LOWEST_PRIORITY 0x1
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#define IOAPIC_PMI 0x2
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#define IOAPIC_NMI 0x4
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#define IOAPIC_INIT 0x5
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#define IOAPIC_EXTINT 0x7
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struct kvm_ioapic {
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u64 base_address;
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u32 ioregsel;
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u32 id;
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u32 irr;
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u32 pad;
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union kvm_ioapic_redirect_entry redirtbl[IOAPIC_NUM_PINS];
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unsigned long irq_states[IOAPIC_NUM_PINS];
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struct kvm_io_device dev;
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struct kvm *kvm;
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void (*ack_notifier)(void *opaque, int irq);
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spinlock_t lock;
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DECLARE_BITMAP(handled_vectors, 256);
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};
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#ifdef DEBUG
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#define ASSERT(x) \
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do { \
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if (!(x)) { \
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printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
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__FILE__, __LINE__, #x); \
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BUG(); \
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} \
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} while (0)
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#else
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#define ASSERT(x) do { } while (0)
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#endif
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static inline struct kvm_ioapic *ioapic_irqchip(struct kvm *kvm)
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{
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return kvm->arch.vioapic;
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}
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int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
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int short_hand, int dest, int dest_mode);
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int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
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void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode);
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bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector);
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int kvm_ioapic_init(struct kvm *kvm);
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void kvm_ioapic_destroy(struct kvm *kvm);
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
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void kvm_ioapic_reset(struct kvm_ioapic *ioapic);
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq);
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int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
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int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state);
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#endif
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