2a7069190e
This patch adds support for the 256k L2 cache found on some IBM/AMCC 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c) which currently "only" adds the L2 cache init code. Other common 4xx stuff can be added later here. The L2 cache handling code is a copy of Eugene's code in arch/ppc with small modifications. Tested on AMCC Taishan 440GX. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
46 lines
1.4 KiB
Makefile
46 lines
1.4 KiB
Makefile
ifeq ($(CONFIG_PPC64),y)
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EXTRA_CFLAGS += -mno-minimal-toc
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endif
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mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
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obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
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obj-$(CONFIG_PPC_MPC106) += grackle.o
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obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
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obj-$(CONFIG_PPC_PMI) += pmi.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_FSL_PCI) += fsl_pci.o
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obj-$(CONFIG_RAPIDIO) += fsl_rio.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
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obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
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mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
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obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
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mv64x60_udbg.o
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obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
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obj-$(CONFIG_AXON_RAM) += axonram.o
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ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_IPIC) += ipic.o
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obj-$(CONFIG_4xx) += uic.o
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obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
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obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
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obj-$(CONFIG_OF_RTC) += of_rtc.o
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ifeq ($(CONFIG_PCI),y)
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obj-$(CONFIG_4xx) += ppc4xx_pci.o
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endif
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endif
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# Temporary hack until we have migrated to asm-powerpc
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ifeq ($(ARCH),powerpc)
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obj-$(CONFIG_CPM) += cpm_common.o
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obj-$(CONFIG_CPM2) += cpm2.o cpm2_pic.o
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obj-$(CONFIG_PPC_DCR) += dcr.o
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obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o
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obj-$(CONFIG_UCODE_PATCH) += micropatch.o
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endif
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