575320d625
This patch introduces a new Kconfig option which, when enabled, causes the kernel to write the PID of the current task into the PROCID field of the CONTEXTIDR on context switch. This is useful when analysing hardware trace, since writes to this register can be configured to emit an event into the trace stream. The thread notifier for writing the PID is deliberately kept separate from the ASID-writing code so that we can support newer processors using LPAE, where the ASID is stored in TTBR0. As such, the switch_mm code is updated to perform a read-modify-write sequence to ensure that we don't clobber the PID on CPUs using the classic 2-level page tables. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
302 lines
8.3 KiB
ArmAsm
302 lines
8.3 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v6.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Modified by Catalin Marinas for noMMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv6 processor support.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define D_CACHE_LINE_SIZE 32
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_IMP (1 << 2)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_WBWA (1 << 3)
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#define TTB_RGN_WT (2 << 3)
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#define TTB_RGN_WB (3 << 3)
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#define TTB_FLAGS_UP TTB_RGN_WBWA
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#define PMD_FLAGS_UP PMD_SECT_WB
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#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
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#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
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ENTRY(cpu_v6_proc_init)
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mov pc, lr
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ENTRY(cpu_v6_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_v6_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_v6_reset)
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x1 @ ...............m
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mcr p15, 0, r1, c1, c0, 0 @ disable MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c5, 4 @ ISB
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mov pc, r0
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ENDPROC(cpu_v6_reset)
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.popsection
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/*
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* cpu_v6_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v6_do_idle)
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mov r1, #0
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mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
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mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
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mov pc, lr
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ENTRY(cpu_v6_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #D_CACHE_LINE_SIZE
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subs r1, r1, #D_CACHE_LINE_SIZE
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bhi 1b
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#endif
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mov pc, lr
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/*
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* cpu_arm926_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v6_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
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ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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mrc p15, 0, r2, c13, c0, 1 @ read current context ID
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bic r2, r2, #0xff @ extract the PID
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and r1, r1, #0xff
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orr r1, r1, r2 @ insert into new context ID
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#endif
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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#endif
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mov pc, lr
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/*
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* cpu_v6_set_pte_ext(ptep, pte, ext)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* (hardware version is stored at -1024 bytes)
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*/
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armv6_mt_table cpu_v6
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ENTRY(cpu_v6_set_pte_ext)
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#ifdef CONFIG_MMU
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armv6_set_pte_ext cpu_v6
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#endif
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mov pc, lr
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/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
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.globl cpu_v6_suspend_size
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.equ cpu_v6_suspend_size, 4 * 6
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#ifdef CONFIG_PM_SLEEP
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ENTRY(cpu_v6_do_suspend)
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stmfd sp!, {r4 - r9, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
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mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
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mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
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mrc p15, 0, r9, c1, c0, 0 @ control register
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stmia r0, {r4 - r9}
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ldmfd sp!, {r4- r9, pc}
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ENDPROC(cpu_v6_do_suspend)
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ENTRY(cpu_v6_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
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mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
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ldmia r0, {r4 - r9}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
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mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
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mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
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mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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mcr p15, 0, ip, c7, c5, 4 @ ISB
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mov r0, r9 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v6_do_resume)
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#endif
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string cpu_v6_name, "ARMv6-compatible processor"
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.align
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__CPUINIT
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/*
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* __v6_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv6 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v6_setup:
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
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ALT_UP(nop)
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orr r0, r0, #0x20
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ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
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ALT_UP(nop)
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#endif
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
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ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
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ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
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ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
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mcr p15, 0, r8, c2, c0, 1 @ load TTB1
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#endif /* CONFIG_MMU */
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adr r5, v6_crval
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ldmia r5, {r5, r6}
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#ifdef CONFIG_CPU_ENDIAN_BE8
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orr r6, r6, #1 << 25 @ big-endian page tables
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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#ifdef CONFIG_ARM_ERRATA_364296
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/*
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* Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
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* corruption with hit-under-miss enabled). The conditional code below
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* (setting the undocumented bit 31 in the auxiliary control register
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* and the FI bit in the control register) disables hit-under-miss
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* without putting the processor into full low interrupt latency mode.
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*/
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ldr r6, =0x4107b362 @ id for ARM1136 r0p2
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mrc p15, 0, r5, c0, c0, 0 @ get processor id
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teq r5, r6 @ check for the faulty core
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mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
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orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
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mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
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orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
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#endif
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mov pc, lr @ return to head.S:__ret
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/*
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* V X F I D LR
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* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
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* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 0 110 0011 1.00 .111 1101 < we want
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*/
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.type v6_crval, #object
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v6_crval:
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crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
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.section ".rodata"
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string cpu_arch_name, "armv6"
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string cpu_elf_name, "v6"
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.align
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.section ".proc.info.init", #alloc, #execinstr
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/*
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* Match any ARMv6 processor core.
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*/
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.type __v6_proc_info, #object
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__v6_proc_info:
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.long 0x0007b000
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.long 0x0007f000
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ALT_SMP(.long \
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PMD_TYPE_SECT | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ | \
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PMD_FLAGS_SMP)
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ALT_UP(.long \
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PMD_TYPE_SECT | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ | \
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PMD_FLAGS_UP)
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __v6_setup
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.long cpu_arch_name
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.long cpu_elf_name
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/* See also feat_v6_fixup() for HWCAP_TLS */
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
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.long cpu_v6_name
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.long v6_processor_functions
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.long v6wbi_tlb_fns
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.long v6_user_fns
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.long v6_cache_fns
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.size __v6_proc_info, . - __v6_proc_info
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