2ca8cf7389
This reworks the context management code used by 4xx,8xx and freescale BookE. It adds support for SMP by implementing a concept of stale context map to lazily flush the TLB on processors where a context may have been invalidated. This also contains the ground work for generalizing such lazy TLB flushing by just picking up a new PID and marking the old one stale. This will be implemented later. This is a first implementation that uses a global spinlock. Ideally, we should try to get at least the fast path (context ID already assigned) lockless or limited to a per context lock, but for now this will do. I tried to keep the UP case reasonably simple to avoid adding too much overhead to 8xx which does a lot of context stealing since it effectively has only 16 PIDs available. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
147 lines
5.8 KiB
C
147 lines
5.8 KiB
C
#ifndef _ASM_POWERPC_MMU_8XX_H_
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#define _ASM_POWERPC_MMU_8XX_H_
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/*
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* PPC8xx support
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*/
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/* Control/status registers for the MPC8xx.
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* A write operation to these registers causes serialized access.
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* During software tablewalk, the registers used perform mask/shift-add
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* operations when written/read. A TLB entry is created when the Mx_RPN
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* is written, and the contents of several registers are used to
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* create the entry.
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*/
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#define SPRN_MI_CTR 784 /* Instruction TLB control register */
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#define MI_GPM 0x80000000 /* Set domain manager mode */
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#define MI_PPM 0x40000000 /* Set subpage protection */
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#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
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#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
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#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
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#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
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#define MI_RESETVAL 0x00000000 /* Value of register at reset */
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1.
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*/
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#define SPRN_MI_AP 786
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#define MI_Ks 0x80000000 /* Should not be set */
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#define MI_Kp 0x40000000 /* Should always be set */
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MI_RPN is written, bits in
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* this register are used to create the TLB entry.
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*/
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#define SPRN_MI_EPN 787
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#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
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#define MI_EVALID 0x00000200 /* Entry is valid */
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#define MI_ASIDMASK 0x0000000f /* ASID match value */
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/* Reset value is undefined */
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the instruction TLB, it contains bits that get loaded into the
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* TLB entry when the MI_RPN is written.
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*/
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#define SPRN_MI_TWC 789
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#define MI_APG 0x000001e0 /* Access protection group (0) */
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#define MI_GUARDED 0x00000010 /* Guarded storage */
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#define MI_PSMASK 0x0000000c /* Mask of page size bits */
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#define MI_PS8MEG 0x0000000c /* 8M page size */
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#define MI_PS512K 0x00000004 /* 512K page size */
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#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
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#define MI_SVALID 0x00000001 /* Segment entry is valid */
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/* Reset value is undefined */
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the instruction TLB, using
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* additional information from the MI_EPN, and MI_TWC registers.
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*/
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#define SPRN_MI_RPN 790
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/* Define an RPN value for mapping kernel memory to large virtual
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* pages for boot initialization. This has real page number of 0,
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* large page size, shared page, cache enabled, and valid.
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* Also mark all subpages valid and write access.
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*/
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#define MI_BOOTINIT 0x000001fd
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#define SPRN_MD_CTR 792 /* Data TLB control register */
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#define MD_GPM 0x80000000 /* Set domain manager mode */
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#define MD_PPM 0x40000000 /* Set subpage protection */
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#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
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#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
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#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
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#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
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#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
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#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
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#define MD_RESETVAL 0x04000000 /* Value of register at reset */
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#define SPRN_M_CASID 793 /* Address space ID (context) to match */
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#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1.
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*/
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#define SPRN_MD_AP 794
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#define MD_Ks 0x80000000 /* Should not be set */
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#define MD_Kp 0x40000000 /* Should always be set */
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MD_RPN is written, bits in
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* this register are used to create the TLB entry.
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*/
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#define SPRN_MD_EPN 795
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#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
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#define MD_EVALID 0x00000200 /* Entry is valid */
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#define MD_ASIDMASK 0x0000000f /* ASID match value */
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/* Reset value is undefined */
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/* The pointer to the base address of the first level page table.
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* During a software tablewalk, reading this register provides the address
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* of the entry associated with MD_EPN.
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*/
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#define SPRN_M_TWB 796
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#define M_L1TB 0xfffff000 /* Level 1 table base address */
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#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
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/* Reset value is undefined */
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the data TLB, it contains bits that get loaded into the TLB entry
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* when the MD_RPN is written. It is also provides the hardware assist
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* for finding the PTE address during software tablewalk.
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*/
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#define SPRN_MD_TWC 797
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#define MD_L2TB 0xfffff000 /* Level 2 table base address */
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#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
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#define MD_APG 0x000001e0 /* Access protection group (0) */
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#define MD_GUARDED 0x00000010 /* Guarded storage */
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#define MD_PSMASK 0x0000000c /* Mask of page size bits */
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#define MD_PS8MEG 0x0000000c /* 8M page size */
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#define MD_PS512K 0x00000004 /* 512K page size */
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#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
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#define MD_WT 0x00000002 /* Use writethrough page attribute */
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#define MD_SVALID 0x00000001 /* Segment entry is valid */
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/* Reset value is undefined */
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the data TLB, using
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* additional information from the MD_EPN, and MD_TWC registers.
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*/
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#define SPRN_MD_RPN 798
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/* This is a temporary storage register that could be used to save
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* a processor working register during a tablewalk.
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*/
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#define SPRN_M_TW 799
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned int id;
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unsigned int active;
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unsigned long vdso_base;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_POWERPC_MMU_8XX_H_ */
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