8fd524b355
This kills bad_dma_address variable, the old mechanism to enable IOMMU drivers to make dma_mapping_error() work in IOMMU's specific way. bad_dma_address variable was introduced to enable IOMMU drivers to make dma_mapping_error() work in IOMMU's specific way. However, it can't handle systems that use both swiotlb and HW IOMMU. SO we introduced dma_map_ops->mapping_error to solve that case. Intel VT-d, GART, and swiotlb already use dma_map_ops->mapping_error. Calgary, AMD IOMMU, and nommu use zero for an error dma address. This adds DMA_ERROR_CODE and converts them to use it (as SPARC and POWER does). Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: muli@il.ibm.com Cc: joerg.roedel@amd.com LKML-Reference: <1258287594-8777-3-git-send-email-fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Ingo Molnar <mingo@elte.hu>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/* Fallback functions when the main IOMMU code is not compiled in. This
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code is roughly equivalent to i386. */
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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static int
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check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
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{
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if (hwdev && !dma_capable(hwdev, bus, size)) {
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if (*hwdev->dma_mask >= DMA_BIT_MASK(32))
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printk(KERN_ERR
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"nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
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name, (long long)bus, size,
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(long long)*hwdev->dma_mask);
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return 0;
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}
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return 1;
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}
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static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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dma_addr_t bus = page_to_phys(page) + offset;
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WARN_ON(size == 0);
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if (!check_addr("map_single", dev, bus, size))
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return DMA_ERROR_CODE;
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flush_write_buffers();
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return bus;
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}
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scatter-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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struct scatterlist *s;
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int i;
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WARN_ON(nents == 0 || sg[0].length == 0);
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for_each_sg(sg, s, nents, i) {
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BUG_ON(!sg_page(s));
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s->dma_address = sg_phys(s);
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if (!check_addr("map_sg", hwdev, s->dma_address, s->length))
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return 0;
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s->dma_length = s->length;
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}
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flush_write_buffers();
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return nents;
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}
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static void nommu_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_addr)
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{
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free_pages((unsigned long)vaddr, get_order(size));
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}
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static void nommu_sync_single_for_device(struct device *dev,
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dma_addr_t addr, size_t size,
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enum dma_data_direction dir)
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{
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flush_write_buffers();
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}
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static void nommu_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction dir)
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{
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flush_write_buffers();
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}
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struct dma_map_ops nommu_dma_ops = {
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.alloc_coherent = dma_generic_alloc_coherent,
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.free_coherent = nommu_free_coherent,
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.map_sg = nommu_map_sg,
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.map_page = nommu_map_page,
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.sync_single_for_device = nommu_sync_single_for_device,
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.sync_sg_for_device = nommu_sync_sg_for_device,
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.is_phys = 1,
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};
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