2e0d232bff
On a SGI Altix TIOCP based PCI bus we need to include the ATE_PIO attribute bit if we're mapping a 32bit MSI address. Signed-off-by: Mike Habeck <habeck@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
151 lines
5.5 KiB
C
151 lines
5.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
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#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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/* Workarounds */
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#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
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#define BUSTYPE_MASK 0x1
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/* Macros given a pcibus structure */
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#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
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#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
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asic == PCIIO_ASIC_TYPE_TIOCP)
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#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
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#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
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/*
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* The different PCI Bridge types supported on the SGI Altix platforms
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*/
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#define PCIBR_BRIDGETYPE_UNKNOWN -1
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#define PCIBR_BRIDGETYPE_PIC 2
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#define PCIBR_BRIDGETYPE_TIOCP 3
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/*
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* Bridge 64bit Direct Map Attributes
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*/
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#define PCI64_ATTR_PREF (1ull << 59)
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#define PCI64_ATTR_PREC (1ull << 58)
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#define PCI64_ATTR_VIRTUAL (1ull << 57)
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#define PCI64_ATTR_BAR (1ull << 56)
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#define PCI64_ATTR_SWAP (1ull << 55)
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#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
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#define PCI32_LOCAL_BASE 0
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#define PCI32_MAPPED_BASE 0x40000000
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#define PCI32_DIRECT_BASE 0x80000000
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#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
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(u64)(x) >= PCI32_MAPPED_BASE)
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#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
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/*
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* Bridge PMU Address Transaltion Entry Attibutes
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*/
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#define PCI32_ATE_V (0x1 << 0)
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#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
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#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
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#define PCI32_ATE_MSI (0x1 << 2)
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#define PCI32_ATE_PREF (0x1 << 3)
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#define PCI32_ATE_BAR (0x1 << 4)
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#define PCI32_ATE_ADDR_SHFT 12
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#define MINIMAL_ATES_REQUIRED(addr, size) \
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(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
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#define MINIMAL_ATE_FLAG(addr, size) \
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(MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
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/* bit 29 of the pci address is the SWAP bit */
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#define ATE_SWAPSHIFT 29
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#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
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#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
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/*
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* I/O page size
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*/
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#if PAGE_SIZE < 16384
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#define IOPFNSHIFT 12 /* 4K per mapped page */
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#else
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#define IOPFNSHIFT 14 /* 16K per mapped page */
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#endif
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#define IOPGSIZE (1 << IOPFNSHIFT)
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#define IOPG(x) ((x) >> IOPFNSHIFT)
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#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
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#define PCIBR_DEV_SWAP_DIR (1ull << 19)
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#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
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/*
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* PMU resources.
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*/
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struct ate_resource{
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u64 *ate;
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u64 num_ate;
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u64 lowest_free_index;
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};
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struct pcibus_info {
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struct pcibus_bussoft pbi_buscommon; /* common header */
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u32 pbi_moduleid;
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short pbi_bridge_type;
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short pbi_bridge_mode;
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struct ate_resource pbi_int_ate_resource;
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u64 pbi_int_ate_size;
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u64 pbi_dir_xbase;
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char pbi_hub_xid;
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u64 pbi_devreg[8];
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u32 pbi_valid_devices;
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u32 pbi_enabled_devices;
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spinlock_t pbi_lock;
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};
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extern int pcibr_init_provider(void);
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extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
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extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
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extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
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extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
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/*
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* prototypes for the bridge asic register access routines in pcibr_reg.c
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*/
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extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
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extern void pcireg_control_bit_set(struct pcibus_info *, u64);
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extern u64 pcireg_tflush_get(struct pcibus_info *);
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extern u64 pcireg_intr_status_get(struct pcibus_info *);
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extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
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extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
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extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
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extern void pcireg_force_intr_set(struct pcibus_info *, int);
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extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
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extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
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extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
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extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
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extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
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extern int pcibr_ate_alloc(struct pcibus_info *, int);
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extern void pcibr_ate_free(struct pcibus_info *, int);
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extern void ate_write(struct pcibus_info *, int, int, u64);
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extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
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void *resp, char **ssdt);
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extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
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int action, void *resp);
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extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
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#endif
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