f5430f9325
Remove bogus reference to "Pentium-II erratum A13" and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
#ifndef _I386_PGALLOC_H
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#define _I386_PGALLOC_H
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#include <linux/threads.h>
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#include <linux/mm.h> /* for struct page */
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#include <linux/pagemap.h>
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#include <asm/tlb.h>
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#include <asm-generic/tlb.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define paravirt_alloc_pt(mm, pfn) do { } while (0)
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#define paravirt_alloc_pd(mm, pfn) do { } while (0)
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#define paravirt_alloc_pd_clone(pfn, clonepfn, start, count) do { } while (0)
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#define paravirt_release_pt(pfn) do { } while (0)
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#define paravirt_release_pd(pfn) do { } while (0)
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#endif
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static inline void pmd_populate_kernel(struct mm_struct *mm,
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pmd_t *pmd, pte_t *pte)
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{
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paravirt_alloc_pt(mm, __pa(pte) >> PAGE_SHIFT);
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set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE));
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}
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static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
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{
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unsigned long pfn = page_to_pfn(pte);
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paravirt_alloc_pt(mm, pfn);
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set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE));
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}
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/*
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* Allocate and free page tables.
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*/
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extern pgd_t *pgd_alloc(struct mm_struct *);
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extern void pgd_free(pgd_t *pgd);
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extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
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extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
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static inline void pte_free_kernel(pte_t *pte)
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{
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free_page((unsigned long)pte);
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}
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static inline void pte_free(struct page *pte)
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{
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__free_page(pte);
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}
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extern void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte);
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#ifdef CONFIG_X86_PAE
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/*
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* In the PAE case we free the pmds as part of the pgd.
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*/
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static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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return (pmd_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
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}
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static inline void pmd_free(pmd_t *pmd)
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{
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BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
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free_page((unsigned long)pmd);
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}
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extern void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
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static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
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{
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paravirt_alloc_pd(mm, __pa(pmd) >> PAGE_SHIFT);
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/* Note: almost everything apart from _PAGE_PRESENT is
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reserved at the pmd (PDPT) level. */
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set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
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/*
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* According to Intel App note "TLBs, Paging-Structure Caches,
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* and Their Invalidation", April 2007, document 317080-001,
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* section 8.1: in PAE mode we explicitly have to flush the
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* TLB via cr3 if the top-level pgd is changed...
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*/
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if (mm == current->active_mm)
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write_cr3(read_cr3());
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}
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#endif /* CONFIG_X86_PAE */
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#endif /* _I386_PGALLOC_H */
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