71de1f8a63
As pointed out by Appalayagari Sreedhar, make sure we include the fix for SPORT hysteresis when reprogramming clocks. Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
159 lines
4.3 KiB
ArmAsm
159 lines
4.3 KiB
ArmAsm
/*
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* File: arch/blackfin/mach-bf548/head.S
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* Based on: arch/blackfin/mach-bf537/head.S
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* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
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*
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* Created: 1998
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* Description: Startup code for Blackfin BF548
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/clocks.h>
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#include <mach/mem_init.h>
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#endif
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.section .l1.text
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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p0.h = hi(VR_CTL);
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p0.l = lo(VR_CTL);
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r0.l = w[p0];
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bitset(r0, 14);
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w[p0] = r0.l;
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ssync;
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p0.h = hi(SIC_IWR0);
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p0.l = lo(SIC_IWR0);
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r0.l = 0x1;
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r0.h = 0x0;
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[p0] = r0;
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SSYNC;
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/*
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* Set PLL_CTL
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* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
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* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
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* - [7] = output delay (add 200ps of delay to mem signals)
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* - [6] = input delay (add 200ps of input delay to mem signals)
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* - [5] = PDWN : 1=All Clocks off
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* - [3] = STOPCK : 1=Core Clock off
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* - [1] = PLL_OFF : 1=Disable Power to PLL
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* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
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* all other bits set to zero
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*/
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p0.h = hi(PLL_LOCKCNT);
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p0.l = lo(PLL_LOCKCNT);
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r0 = 0x300(Z);
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w[p0] = r0.l;
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ssync;
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/* enable self refresh via SRREQ */
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P2.H = hi(EBIU_RSTCTL);
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P2.L = lo(EBIU_RSTCTL);
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R0 = [P2];
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BITSET (R0, 3);
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[P2] = R0;
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SSYNC;
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/* wait for SRACK bit to be set */
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.LSRR_MODE:
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R0 = [P2];
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CC = BITTST(R0, 4);
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if !CC JUMP .LSRR_MODE;
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r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
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r0 = r0 << 9; /* Shift it over, */
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r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
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r0 = r1 | r0;
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r1 = PLL_BYPASS; /* Bypass the PLL? */
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r1 = r1 << 8; /* Shift it over */
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r0 = r1 | r0; /* add them all together */
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#ifdef ANOMALY_05000265
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r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
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#endif
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p0.h = hi(PLL_CTL);
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p0.l = lo(PLL_CTL); /* Load the address */
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cli r2; /* Disable interrupts */
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ssync;
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w[p0] = r0.l; /* Set the value */
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idle; /* Wait for the PLL to stablize */
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sti r2; /* Enable interrupts */
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.Lcheck_again:
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p0.h = hi(PLL_STAT);
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p0.l = lo(PLL_STAT);
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R0 = W[P0](Z);
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CC = BITTST(R0,5);
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if ! CC jump .Lcheck_again;
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/* Configure SCLK & CCLK Dividers */
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r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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p0.h = hi(PLL_DIV);
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p0.l = lo(PLL_DIV);
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w[p0] = r0.l;
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ssync;
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/* disable self refresh by clearing SRREQ */
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P2.H = hi(EBIU_RSTCTL);
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P2.L = lo(EBIU_RSTCTL);
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R0 = [P2];
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CC = BITTST(R0, 0);
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if CC jump .Lskipddrrst;
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BITSET (R0, 0);
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.Lskipddrrst:
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BITCLR (R0, 3);
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[P2] = R0;
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SSYNC;
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p0.l = lo(EBIU_DDRCTL0);
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p0.h = hi(EBIU_DDRCTL0);
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r0.l = lo(mem_DDRCTL0);
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r0.h = hi(mem_DDRCTL0);
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[p0] = r0;
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ssync;
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p0.l = lo(EBIU_DDRCTL1);
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p0.h = hi(EBIU_DDRCTL1);
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r0.l = lo(mem_DDRCTL1);
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r0.h = hi(mem_DDRCTL1);
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[p0] = r0;
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ssync;
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p0.l = lo(EBIU_DDRCTL2);
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p0.h = hi(EBIU_DDRCTL2);
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r0.l = lo(mem_DDRCTL2);
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r0.h = hi(mem_DDRCTL2);
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[p0] = r0;
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ssync;
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RTS;
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ENDPROC(_start_dma_code)
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#endif /* CONFIG_BFIN_KERNEL_CLOCK */
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