9702785a74
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
292 lines
8.8 KiB
ArmAsm
292 lines
8.8 KiB
ArmAsm
/*
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Asm versions of Xen pv-ops, suitable for either direct use or inlining.
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The inline versions are the same as the direct-use versions, with the
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pre- and post-amble chopped off.
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This code is encoded for size rather than absolute efficiency,
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with a view to being able to inline as much as possible.
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We only bother with direct forms (ie, vcpu in pda) of the operations
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here; the indirect forms are better handled in C, since they're
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generally too large to inline anyway.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/percpu.h>
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#include <asm/processor-flags.h>
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#include <asm/segment.h>
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#include <xen/interface/xen.h>
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#define RELOC(x, v) .globl x##_reloc; x##_reloc=v
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#define ENDPATCH(x) .globl x##_end; x##_end=.
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/* Pseudo-flag used for virtual NMI, which we don't implement yet */
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#define XEN_EFLAGS_NMI 0x80000000
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/*
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Enable events. This clears the event mask and tests the pending
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event status with one and operation. If there are pending
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events, then enter the hypervisor to get them handled.
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*/
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ENTRY(xen_irq_enable_direct)
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/* Clear mask and test pending */
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andw $0x00ff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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jz 1f
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2: call check_events
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1:
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ENDPATCH(xen_irq_enable_direct)
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ret
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ENDPROC(xen_irq_enable_direct)
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RELOC(xen_irq_enable_direct, 2b+1)
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/*
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Disabling events is simply a matter of making the event mask
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non-zero.
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*/
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ENTRY(xen_irq_disable_direct)
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movb $1, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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ENDPATCH(xen_irq_disable_direct)
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ret
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ENDPROC(xen_irq_disable_direct)
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RELOC(xen_irq_disable_direct, 0)
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/*
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(xen_)save_fl is used to get the current interrupt enable status.
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Callers expect the status to be in X86_EFLAGS_IF, and other bits
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may be set in the return value. We take advantage of this by
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making sure that X86_EFLAGS_IF has the right value (and other bits
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in that byte are 0), but other bits in the return value are
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undefined. We need to toggle the state of the bit, because
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Xen and x86 use opposite senses (mask vs enable).
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*/
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ENTRY(xen_save_fl_direct)
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testb $0xff, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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setz %ah
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addb %ah,%ah
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ENDPATCH(xen_save_fl_direct)
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ret
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ENDPROC(xen_save_fl_direct)
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RELOC(xen_save_fl_direct, 0)
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/*
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In principle the caller should be passing us a value return
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from xen_save_fl_direct, but for robustness sake we test only
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the X86_EFLAGS_IF flag rather than the whole byte. After
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setting the interrupt mask state, it checks for unmasked
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pending events and enters the hypervisor to get them delivered
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if so.
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*/
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ENTRY(xen_restore_fl_direct)
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testb $X86_EFLAGS_IF>>8, %ah
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setz PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_mask
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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/* check for unmasked and pending */
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cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info)+XEN_vcpu_info_pending
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jz 1f
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2: call check_events
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1:
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ENDPATCH(xen_restore_fl_direct)
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ret
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ENDPROC(xen_restore_fl_direct)
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RELOC(xen_restore_fl_direct, 2b+1)
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/*
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This is run where a normal iret would be run, with the same stack setup:
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8: eflags
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4: cs
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esp-> 0: eip
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This attempts to make sure that any pending events are dealt
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with on return to usermode, but there is a small window in
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which an event can happen just before entering usermode. If
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the nested interrupt ends up setting one of the TIF_WORK_MASK
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pending work flags, they will not be tested again before
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returning to usermode. This means that a process can end up
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with pending work, which will be unprocessed until the process
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enters and leaves the kernel again, which could be an
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unbounded amount of time. This means that a pending signal or
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reschedule event could be indefinitely delayed.
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The fix is to notice a nested interrupt in the critical
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window, and if one occurs, then fold the nested interrupt into
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the current interrupt stack frame, and re-process it
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iteratively rather than recursively. This means that it will
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exit via the normal path, and all pending work will be dealt
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with appropriately.
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Because the nested interrupt handler needs to deal with the
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current stack state in whatever form its in, we keep things
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simple by only using a single register which is pushed/popped
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on the stack.
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Non-direct iret could be done in the same way, but it would
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require an annoying amount of code duplication. We'll assume
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that direct mode will be the common case once the hypervisor
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support becomes commonplace.
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*/
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ENTRY(xen_iret_direct)
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/* test eflags for special cases */
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testl $(X86_EFLAGS_VM | XEN_EFLAGS_NMI), 8(%esp)
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jnz hyper_iret
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push %eax
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ESP_OFFSET=4 # bytes pushed onto stack
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/* Store vcpu_info pointer for easy access. Do it this
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way to avoid having to reload %fs */
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#ifdef CONFIG_SMP
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GET_THREAD_INFO(%eax)
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movl TI_cpu(%eax),%eax
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movl __per_cpu_offset(,%eax,4),%eax
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lea per_cpu__xen_vcpu_info(%eax),%eax
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#else
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movl $per_cpu__xen_vcpu_info, %eax
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#endif
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/* check IF state we're restoring */
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testb $X86_EFLAGS_IF>>8, 8+1+ESP_OFFSET(%esp)
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/* Maybe enable events. Once this happens we could get a
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recursive event, so the critical region starts immediately
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afterwards. However, if that happens we don't end up
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resuming the code, so we don't have to be worried about
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being preempted to another CPU. */
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setz XEN_vcpu_info_mask(%eax)
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xen_iret_start_crit:
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/* check for unmasked and pending */
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cmpw $0x0001, XEN_vcpu_info_pending(%eax)
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/* If there's something pending, mask events again so we
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can jump back into xen_hypervisor_callback */
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sete XEN_vcpu_info_mask(%eax)
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popl %eax
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/* From this point on the registers are restored and the stack
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updated, so we don't need to worry about it if we're preempted */
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iret_restore_end:
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/* Jump to hypervisor_callback after fixing up the stack.
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Events are masked, so jumping out of the critical
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region is OK. */
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je xen_hypervisor_callback
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iret
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xen_iret_end_crit:
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hyper_iret:
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/* put this out of line since its very rarely used */
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jmp hypercall_page + __HYPERVISOR_iret * 32
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.globl xen_iret_start_crit, xen_iret_end_crit
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/*
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This is called by xen_hypervisor_callback in entry.S when it sees
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that the EIP at the time of interrupt was between xen_iret_start_crit
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and xen_iret_end_crit. We're passed the EIP in %eax so we can do
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a more refined determination of what to do.
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The stack format at this point is:
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----------------
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ss : (ss/esp may be present if we came from usermode)
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esp :
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eflags } outer exception info
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cs }
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eip }
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---------------- <- edi (copy dest)
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eax : outer eax if it hasn't been restored
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----------------
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eflags } nested exception info
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cs } (no ss/esp because we're nested
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eip } from the same ring)
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orig_eax }<- esi (copy src)
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- - - - - - - -
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fs }
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es }
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ds } SAVE_ALL state
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eax }
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: :
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ebx }
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----------------
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return addr <- esp
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----------------
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In order to deliver the nested exception properly, we need to shift
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everything from the return addr up to the error code so it
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sits just under the outer exception info. This means that when we
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handle the exception, we do it in the context of the outer exception
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rather than starting a new one.
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The only caveat is that if the outer eax hasn't been
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restored yet (ie, it's still on stack), we need to insert
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its value into the SAVE_ALL state before going on, since
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it's usermode state which we eventually need to restore.
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*/
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ENTRY(xen_iret_crit_fixup)
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/* offsets +4 for return address */
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/*
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Paranoia: Make sure we're really coming from userspace.
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One could imagine a case where userspace jumps into the
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critical range address, but just before the CPU delivers a GP,
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it decides to deliver an interrupt instead. Unlikely?
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Definitely. Easy to avoid? Yes. The Intel documents
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explicitly say that the reported EIP for a bad jump is the
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jump instruction itself, not the destination, but some virtual
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environments get this wrong.
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*/
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movl PT_CS+4(%esp), %ecx
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andl $SEGMENT_RPL_MASK, %ecx
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cmpl $USER_RPL, %ecx
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je 2f
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lea PT_ORIG_EAX+4(%esp), %esi
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lea PT_EFLAGS+4(%esp), %edi
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/* If eip is before iret_restore_end then stack
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hasn't been restored yet. */
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cmp $iret_restore_end, %eax
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jae 1f
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movl 0+4(%edi),%eax /* copy EAX */
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movl %eax, PT_EAX+4(%esp)
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lea ESP_OFFSET(%edi),%edi /* move dest up over saved regs */
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/* set up the copy */
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1: std
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mov $(PT_EIP+4) / 4, %ecx /* copy ret+saved regs up to orig_eax */
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rep movsl
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cld
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lea 4(%edi),%esp /* point esp to new frame */
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2: ret
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/*
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Force an event check by making a hypercall,
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but preserve regs before making the call.
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*/
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check_events:
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push %eax
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push %ecx
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push %edx
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call force_evtchn_callback
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pop %edx
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pop %ecx
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pop %eax
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ret
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