342 lines
8.4 KiB
C
342 lines
8.4 KiB
C
/*
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* Dynamic DMA mapping support.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/proto.h>
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#include <asm/calgary.h>
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int iommu_merge __read_mostly = 0;
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EXPORT_SYMBOL(iommu_merge);
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dma_addr_t bad_dma_address __read_mostly;
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EXPORT_SYMBOL(bad_dma_address);
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/* This tells the BIO block layer to assume merging. Default to off
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because we cannot guarantee merging later. */
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int iommu_bio_merge __read_mostly = 0;
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EXPORT_SYMBOL(iommu_bio_merge);
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int iommu_sac_force __read_mostly = 0;
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EXPORT_SYMBOL(iommu_sac_force);
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int no_iommu __read_mostly;
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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#else
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int panic_on_overflow __read_mostly = 0;
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int force_iommu __read_mostly= 0;
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#endif
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/* Set this to 1 if there is a HW IOMMU in the system */
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int iommu_detected __read_mostly = 0;
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/* Dummy device used for NULL arguments (normally ISA). Better would
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be probably a smaller DMA mask, but this is bug-to-bug compatible
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to i386. */
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struct device fallback_dev = {
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.bus_id = "fallback device",
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.coherent_dma_mask = DMA_32BIT_MASK,
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.dma_mask = &fallback_dev.coherent_dma_mask,
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};
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/* Allocate DMA memory on node near device */
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noinline static void *
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dma_alloc_pages(struct device *dev, gfp_t gfp, unsigned order)
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{
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struct page *page;
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int node;
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#ifdef CONFIG_PCI
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if (dev->bus == &pci_bus_type)
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node = pcibus_to_node(to_pci_dev(dev)->bus);
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else
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#endif
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node = numa_node_id();
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if (node < first_node(node_online_map))
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node = first_node(node_online_map);
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page = alloc_pages_node(node, gfp, order);
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return page ? page_address(page) : NULL;
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}
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/*
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* Allocate memory for a coherent mapping.
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*/
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void *
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dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp)
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{
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void *memory;
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unsigned long dma_mask = 0;
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u64 bus;
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if (!dev)
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dev = &fallback_dev;
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dma_mask = dev->coherent_dma_mask;
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if (dma_mask == 0)
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dma_mask = DMA_32BIT_MASK;
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/* Don't invoke OOM killer */
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gfp |= __GFP_NORETRY;
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/* Kludge to make it bug-to-bug compatible with i386. i386
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uses the normal dma_mask for alloc_coherent. */
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dma_mask &= *dev->dma_mask;
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/* Why <=? Even when the mask is smaller than 4GB it is often
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larger than 16MB and in this case we have a chance of
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finding fitting memory in the next higher zone first. If
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not retry with true GFP_DMA. -AK */
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if (dma_mask <= DMA_32BIT_MASK)
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gfp |= GFP_DMA32;
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again:
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memory = dma_alloc_pages(dev, gfp, get_order(size));
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if (memory == NULL)
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return NULL;
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{
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int high, mmu;
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bus = virt_to_bus(memory);
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high = (bus + size) >= dma_mask;
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mmu = high;
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if (force_iommu && !(gfp & GFP_DMA))
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mmu = 1;
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else if (high) {
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free_pages((unsigned long)memory,
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get_order(size));
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/* Don't use the 16MB ZONE_DMA unless absolutely
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needed. It's better to use remapping first. */
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if (dma_mask < DMA_32BIT_MASK && !(gfp & GFP_DMA)) {
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gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
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goto again;
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}
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/* Let low level make its own zone decisions */
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gfp &= ~(GFP_DMA32|GFP_DMA);
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if (dma_ops->alloc_coherent)
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return dma_ops->alloc_coherent(dev, size,
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dma_handle, gfp);
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return NULL;
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}
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memset(memory, 0, size);
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if (!mmu) {
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*dma_handle = virt_to_bus(memory);
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return memory;
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}
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}
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if (dma_ops->alloc_coherent) {
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free_pages((unsigned long)memory, get_order(size));
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gfp &= ~(GFP_DMA|GFP_DMA32);
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return dma_ops->alloc_coherent(dev, size, dma_handle, gfp);
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}
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if (dma_ops->map_simple) {
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*dma_handle = dma_ops->map_simple(dev, memory,
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size,
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PCI_DMA_BIDIRECTIONAL);
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if (*dma_handle != bad_dma_address)
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return memory;
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}
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if (panic_on_overflow)
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panic("dma_alloc_coherent: IOMMU overflow by %lu bytes\n",size);
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free_pages((unsigned long)memory, get_order(size));
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return NULL;
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}
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EXPORT_SYMBOL(dma_alloc_coherent);
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/*
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* Unmap coherent memory.
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* The caller must ensure that the device has finished accessing the mapping.
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*/
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void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t bus)
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{
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if (dma_ops->unmap_single)
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dma_ops->unmap_single(dev, bus, size, 0);
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free_pages((unsigned long)vaddr, get_order(size));
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}
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EXPORT_SYMBOL(dma_free_coherent);
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static int forbid_dac __read_mostly;
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int dma_supported(struct device *dev, u64 mask)
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{
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#ifdef CONFIG_PCI
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if (mask > 0xffffffff && forbid_dac > 0) {
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printk(KERN_INFO "PCI: Disallowing DAC for device %s\n", dev->bus_id);
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return 0;
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}
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#endif
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if (dma_ops->dma_supported)
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return dma_ops->dma_supported(dev, mask);
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/* Copied from i386. Doesn't make much sense, because it will
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only work for pci_alloc_coherent.
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The caller just has to use GFP_DMA in this case. */
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if (mask < DMA_24BIT_MASK)
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return 0;
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/* Tell the device to use SAC when IOMMU force is on. This
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allows the driver to use cheaper accesses in some cases.
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Problem with this is that if we overflow the IOMMU area and
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return DAC as fallback address the device may not handle it
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correctly.
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As a special case some controllers have a 39bit address
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mode that is as efficient as 32bit (aic79xx). Don't force
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SAC for these. Assume all masks <= 40 bits are of this
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type. Normally this doesn't make any difference, but gives
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more gentle handling of IOMMU overflow. */
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if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
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printk(KERN_INFO "%s: Force SAC with mask %Lx\n", dev->bus_id,mask);
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return 0;
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}
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return 1;
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}
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EXPORT_SYMBOL(dma_supported);
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int dma_set_mask(struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_mask);
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/* iommu=[size][,noagp][,off][,force][,noforce][,leak][,memaper[=order]][,merge]
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[,forcesac][,fullflush][,nomerge][,biomerge]
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size set size of iommu (in bytes)
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noagp don't initialize the AGP driver and use full aperture.
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off don't use the IOMMU
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leak turn on simple iommu leak tracing (only when CONFIG_IOMMU_LEAK is on)
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memaper[=order] allocate an own aperture over RAM with size 32MB^order.
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noforce don't force IOMMU usage. Default.
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force Force IOMMU.
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merge Do lazy merging. This may improve performance on some block devices.
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Implies force (experimental)
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biomerge Do merging at the BIO layer. This is more efficient than merge,
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but should be only done with very big IOMMUs. Implies merge,force.
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nomerge Don't do SG merging.
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forcesac For SAC mode for masks <40bits (experimental)
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fullflush Flush IOMMU on each allocation (default)
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nofullflush Don't use IOMMU fullflush
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allowed overwrite iommu off workarounds for specific chipsets.
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soft Use software bounce buffering (default for Intel machines)
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noaperture Don't touch the aperture for AGP.
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allowdac Allow DMA >4GB
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nodac Forbid DMA >4GB
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panic Force panic when IOMMU overflows
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*/
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__init int iommu_setup(char *p)
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{
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iommu_merge = 1;
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if (!p)
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return -EINVAL;
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while (*p) {
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if (!strncmp(p,"off",3))
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no_iommu = 1;
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/* gart_parse_options has more force support */
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if (!strncmp(p,"force",5))
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force_iommu = 1;
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if (!strncmp(p,"noforce",7)) {
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iommu_merge = 0;
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force_iommu = 0;
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}
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if (!strncmp(p, "biomerge",8)) {
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iommu_bio_merge = 4096;
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "panic",5))
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panic_on_overflow = 1;
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if (!strncmp(p, "nopanic",7))
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panic_on_overflow = 0;
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if (!strncmp(p, "merge",5)) {
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "nomerge",7))
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iommu_merge = 0;
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if (!strncmp(p, "forcesac",8))
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iommu_sac_force = 1;
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if (!strncmp(p, "allowdac", 8))
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forbid_dac = 0;
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if (!strncmp(p, "nodac", 5))
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forbid_dac = -1;
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#ifdef CONFIG_SWIOTLB
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if (!strncmp(p, "soft",4))
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swiotlb = 1;
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#endif
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#ifdef CONFIG_IOMMU
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gart_parse_options(p);
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#endif
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p += strcspn(p, ",");
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if (*p == ',')
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++p;
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}
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return 0;
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}
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early_param("iommu", iommu_setup);
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void __init pci_iommu_alloc(void)
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{
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/*
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* The order of these functions is important for
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* fall-back/fail-over reasons
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*/
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#ifdef CONFIG_IOMMU
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iommu_hole_init();
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#endif
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#ifdef CONFIG_CALGARY_IOMMU
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detect_calgary();
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#endif
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#ifdef CONFIG_SWIOTLB
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pci_swiotlb_init();
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#endif
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}
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static int __init pci_iommu_init(void)
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{
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#ifdef CONFIG_CALGARY_IOMMU
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calgary_iommu_init();
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#endif
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#ifdef CONFIG_IOMMU
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gart_iommu_init();
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#endif
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no_iommu_init();
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return 0;
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}
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/* Must execute after PCI subsystem */
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fs_initcall(pci_iommu_init);
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