04b5d028f5
- wrap calls into cxgb3 and fail them if we're in the middle of a PCI EEH event. - correctly unwind and release endpoint and other resources when we are in an EEH event. - dispatch IB_EVENT_DEVICE_FATAL event when cxgb3 notifies iw_cxgb3 of a fatal error. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
208 lines
5.8 KiB
C
208 lines
5.8 KiB
C
/*
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* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <rdma/ib_verbs.h>
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#include "cxgb3_offload.h"
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#include "iwch_provider.h"
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#include "iwch_user.h"
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#include "iwch.h"
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#include "iwch_cm.h"
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#define DRV_VERSION "1.1"
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MODULE_AUTHOR("Boyd Faulkner, Steve Wise");
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MODULE_DESCRIPTION("Chelsio T3 RDMA Driver");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_VERSION(DRV_VERSION);
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cxgb3_cpl_handler_func t3c_handlers[NUM_CPL_CMDS];
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static void open_rnic_dev(struct t3cdev *);
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static void close_rnic_dev(struct t3cdev *);
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static void iwch_err_handler(struct t3cdev *, u32, u32);
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struct cxgb3_client t3c_client = {
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.name = "iw_cxgb3",
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.add = open_rnic_dev,
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.remove = close_rnic_dev,
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.handlers = t3c_handlers,
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.redirect = iwch_ep_redirect,
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.err_handler = iwch_err_handler
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};
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static LIST_HEAD(dev_list);
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static DEFINE_MUTEX(dev_mutex);
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static void rnic_init(struct iwch_dev *rnicp)
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{
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PDBG("%s iwch_dev %p\n", __func__, rnicp);
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idr_init(&rnicp->cqidr);
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idr_init(&rnicp->qpidr);
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idr_init(&rnicp->mmidr);
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spin_lock_init(&rnicp->lock);
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rnicp->attr.max_qps = T3_MAX_NUM_QP - 32;
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rnicp->attr.max_wrs = T3_MAX_QP_DEPTH;
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rnicp->attr.max_sge_per_wr = T3_MAX_SGE;
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rnicp->attr.max_sge_per_rdma_write_wr = T3_MAX_SGE;
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rnicp->attr.max_cqs = T3_MAX_NUM_CQ - 1;
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rnicp->attr.max_cqes_per_cq = T3_MAX_CQ_DEPTH;
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rnicp->attr.max_mem_regs = cxio_num_stags(&rnicp->rdev);
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rnicp->attr.max_phys_buf_entries = T3_MAX_PBL_SIZE;
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rnicp->attr.max_pds = T3_MAX_NUM_PD - 1;
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rnicp->attr.mem_pgsizes_bitmask = T3_PAGESIZE_MASK;
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rnicp->attr.max_mr_size = T3_MAX_MR_SIZE;
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rnicp->attr.can_resize_wq = 0;
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rnicp->attr.max_rdma_reads_per_qp = 8;
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rnicp->attr.max_rdma_read_resources =
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rnicp->attr.max_rdma_reads_per_qp * rnicp->attr.max_qps;
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rnicp->attr.max_rdma_read_qp_depth = 8; /* IRD */
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rnicp->attr.max_rdma_read_depth =
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rnicp->attr.max_rdma_read_qp_depth * rnicp->attr.max_qps;
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rnicp->attr.rq_overflow_handled = 0;
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rnicp->attr.can_modify_ird = 0;
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rnicp->attr.can_modify_ord = 0;
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rnicp->attr.max_mem_windows = rnicp->attr.max_mem_regs - 1;
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rnicp->attr.stag0_value = 1;
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rnicp->attr.zbva_support = 1;
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rnicp->attr.local_invalidate_fence = 1;
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rnicp->attr.cq_overflow_detection = 1;
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return;
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}
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static void open_rnic_dev(struct t3cdev *tdev)
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{
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struct iwch_dev *rnicp;
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static int vers_printed;
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PDBG("%s t3cdev %p\n", __func__, tdev);
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if (!vers_printed++)
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printk(KERN_INFO MOD "Chelsio T3 RDMA Driver - version %s\n",
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DRV_VERSION);
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rnicp = (struct iwch_dev *)ib_alloc_device(sizeof(*rnicp));
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if (!rnicp) {
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printk(KERN_ERR MOD "Cannot allocate ib device\n");
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return;
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}
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rnicp->rdev.ulp = rnicp;
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rnicp->rdev.t3cdev_p = tdev;
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mutex_lock(&dev_mutex);
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if (cxio_rdev_open(&rnicp->rdev)) {
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mutex_unlock(&dev_mutex);
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printk(KERN_ERR MOD "Unable to open CXIO rdev\n");
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ib_dealloc_device(&rnicp->ibdev);
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return;
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}
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rnic_init(rnicp);
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list_add_tail(&rnicp->entry, &dev_list);
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mutex_unlock(&dev_mutex);
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if (iwch_register_device(rnicp)) {
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printk(KERN_ERR MOD "Unable to register device\n");
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close_rnic_dev(tdev);
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}
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printk(KERN_INFO MOD "Initialized device %s\n",
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pci_name(rnicp->rdev.rnic_info.pdev));
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return;
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}
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static void close_rnic_dev(struct t3cdev *tdev)
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{
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struct iwch_dev *dev, *tmp;
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PDBG("%s t3cdev %p\n", __func__, tdev);
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mutex_lock(&dev_mutex);
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list_for_each_entry_safe(dev, tmp, &dev_list, entry) {
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if (dev->rdev.t3cdev_p == tdev) {
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list_del(&dev->entry);
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iwch_unregister_device(dev);
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cxio_rdev_close(&dev->rdev);
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idr_destroy(&dev->cqidr);
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idr_destroy(&dev->qpidr);
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idr_destroy(&dev->mmidr);
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ib_dealloc_device(&dev->ibdev);
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break;
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}
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}
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mutex_unlock(&dev_mutex);
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}
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static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error)
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{
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struct cxio_rdev *rdev = tdev->ulp;
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struct iwch_dev *rnicp = rdev_to_iwch_dev(rdev);
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struct ib_event event;
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if (status == OFFLOAD_STATUS_DOWN) {
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rdev->flags = CXIO_ERROR_FATAL;
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event.device = &rnicp->ibdev;
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event.event = IB_EVENT_DEVICE_FATAL;
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event.element.port_num = 0;
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ib_dispatch_event(&event);
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}
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return;
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}
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static int __init iwch_init_module(void)
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{
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int err;
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err = cxio_hal_init();
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if (err)
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return err;
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err = iwch_cm_init();
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if (err)
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return err;
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cxio_register_ev_cb(iwch_ev_dispatch);
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cxgb3_register_client(&t3c_client);
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return 0;
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}
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static void __exit iwch_exit_module(void)
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{
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cxgb3_unregister_client(&t3c_client);
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cxio_unregister_ev_cb(iwch_ev_dispatch);
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iwch_cm_term();
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cxio_hal_exit();
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}
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module_init(iwch_init_module);
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module_exit(iwch_exit_module);
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