9666f4009c
Reimplement suspend/resume support using sdev->manage_start_stop. * Device suspend/resume is now SCSI layer's responsibility and the code is simplified a lot. * DPM is dropped. This also simplifies code a lot. Suspend/resume status is port-wide now. * ata_scsi_device_suspend/resume() and ata_dev_ready() removed. * Resume now has to wait for disk to spin up before proceeding. I couldn't find easy way out as libata is in EH waiting for the disk to be ready and sd is waiting for EH to complete to issue START_STOP. * sdev->manage_start_stop is set to 1 in ata_scsi_slave_config(). This fixes spindown on shutdown and suspend-to-disk. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
504 lines
13 KiB
C
504 lines
13 KiB
C
/*
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* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
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*
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* This driver is heavily based upon:
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*
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* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2003 Red Hat Inc
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*
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*
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* TODO
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* Maybe PLL mode
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* Look into engine reset on timeout errors. Should not be
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* required.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt366"
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#define DRV_VERSION "0.6.1"
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struct hpt_clock {
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u8 xfer_speed;
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u32 timing;
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};
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/* key for bus clock timings
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* bit
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* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
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* register access.
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* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
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* register access.
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* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
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* during task file register access.
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* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
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* xfer.
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* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
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* register access.
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* 28 UDMA enable
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* 29 DMA enable
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* 30 PIO_MST enable. if set, the chip is in bus master mode during
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* PIO.
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* 31 FIFO enable.
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*/
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static const struct hpt_clock hpt366_40[] = {
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{ XFER_UDMA_4, 0x900fd943 },
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{ XFER_UDMA_3, 0x900ad943 },
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{ XFER_UDMA_2, 0x900bd943 },
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{ XFER_UDMA_1, 0x9008d943 },
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{ XFER_UDMA_0, 0x9008d943 },
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{ XFER_MW_DMA_2, 0xa008d943 },
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{ XFER_MW_DMA_1, 0xa010d955 },
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{ XFER_MW_DMA_0, 0xa010d9fc },
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{ XFER_PIO_4, 0xc008d963 },
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{ XFER_PIO_3, 0xc010d974 },
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{ XFER_PIO_2, 0xc010d997 },
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{ XFER_PIO_1, 0xc010d9c7 },
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{ XFER_PIO_0, 0xc018d9d9 },
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{ 0, 0x0120d9d9 }
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};
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static const struct hpt_clock hpt366_33[] = {
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{ XFER_UDMA_4, 0x90c9a731 },
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{ XFER_UDMA_3, 0x90cfa731 },
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{ XFER_UDMA_2, 0x90caa731 },
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{ XFER_UDMA_1, 0x90cba731 },
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{ XFER_UDMA_0, 0x90c8a731 },
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{ XFER_MW_DMA_2, 0xa0c8a731 },
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{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
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{ XFER_MW_DMA_0, 0xa0c8a797 },
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{ XFER_PIO_4, 0xc0c8a731 },
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{ XFER_PIO_3, 0xc0c8a742 },
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{ XFER_PIO_2, 0xc0d0a753 },
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{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
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{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
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{ 0, 0x0120a7a7 }
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};
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static const struct hpt_clock hpt366_25[] = {
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{ XFER_UDMA_4, 0x90c98521 },
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{ XFER_UDMA_3, 0x90cf8521 },
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{ XFER_UDMA_2, 0x90cf8521 },
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{ XFER_UDMA_1, 0x90cb8521 },
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{ XFER_UDMA_0, 0x90cb8521 },
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{ XFER_MW_DMA_2, 0xa0ca8521 },
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{ XFER_MW_DMA_1, 0xa0ca8532 },
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{ XFER_MW_DMA_0, 0xa0ca8575 },
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{ XFER_PIO_4, 0xc0ca8521 },
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{ XFER_PIO_3, 0xc0ca8532 },
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{ XFER_PIO_2, 0xc0ca8542 },
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{ XFER_PIO_1, 0xc0d08572 },
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{ XFER_PIO_0, 0xc0d08585 },
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{ 0, 0x01208585 }
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};
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static const char *bad_ata33[] = {
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"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
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"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
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"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
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"Maxtor 90510D4",
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"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
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"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
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"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
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NULL
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};
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static const char *bad_ata66_4[] = {
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"IBM-DTLA-307075",
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"IBM-DTLA-307060",
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"IBM-DTLA-307045",
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"IBM-DTLA-307030",
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"IBM-DTLA-307020",
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"IBM-DTLA-307015",
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"IBM-DTLA-305040",
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"IBM-DTLA-305030",
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"IBM-DTLA-305020",
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"IC35L010AVER07-0",
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"IC35L020AVER07-0",
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"IC35L030AVER07-0",
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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NULL
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};
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static const char *bad_ata66_3[] = {
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"WDC AC310200R",
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NULL
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};
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static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
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{
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unsigned char model_num[ATA_ID_PROD_LEN + 1];
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int i = 0;
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
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while (list[i] != NULL) {
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if (!strcmp(list[i], model_num)) {
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printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
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modestr, list[i]);
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return 1;
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}
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i++;
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}
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return 0;
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}
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/**
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* hpt366_filter - mode selection filter
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* @adev: ATA device
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*
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* Block UDMA on devices that cause trouble with this controller.
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*/
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static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
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{
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if (adev->class == ATA_DEV_ATA) {
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if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
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mask &= ~ATA_MASK_UDMA;
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if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
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mask &= ~(0x07 << ATA_SHIFT_UDMA);
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if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
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mask &= ~(0x0F << ATA_SHIFT_UDMA);
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}
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return ata_pci_default_filter(adev, mask);
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}
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/**
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* hpt36x_find_mode - reset the hpt36x bus
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* @ap: ATA port
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* @speed: transfer mode
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*
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* Return the 32bit register programming information for this channel
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* that matches the speed provided.
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*/
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static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
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{
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struct hpt_clock *clocks = ap->host->private_data;
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while(clocks->xfer_speed) {
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if (clocks->xfer_speed == speed)
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return clocks->timing;
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clocks++;
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}
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BUG();
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return 0xffffffffU; /* silence compiler warning */
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}
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static int hpt36x_cable_detect(struct ata_port *ap)
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{
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u8 ata66;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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pci_read_config_byte(pdev, 0x5A, &ata66);
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if (ata66 & (1 << ap->port_no))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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static int hpt36x_pre_reset(struct ata_port *ap, unsigned long deadline)
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{
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static const struct pci_bits hpt36x_enable_bits[] = {
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{ 0x50, 1, 0x04, 0x04 },
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{ 0x54, 1, 0x04, 0x04 }
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_std_prereset(ap, deadline);
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}
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/**
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* hpt36x_error_handler - reset the hpt36x bus
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* @ap: ATA port to reset
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*
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* Perform the reset handling for the 366/368
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*/
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static void hpt36x_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* hpt366_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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* Perform PIO mode setup.
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*/
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static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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if (fast & 0x80) {
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fast &= ~0x80;
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pci_write_config_byte(pdev, addr2, fast);
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}
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt36x_find_mode(ap, adev->pio_mode);
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mode &= ~0x8000000; /* No FIFO in PIO */
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mode &= ~0x30070000; /* Leave config bits alone */
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reg &= 0x30070000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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/**
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* hpt366_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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* Set up the channel for MWDMA or UDMA modes. Much the same as with
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* PIO, load the mode number and then set MWDMA or UDMA flag.
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*/
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static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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if (fast & 0x80) {
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fast &= ~0x80;
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pci_write_config_byte(pdev, addr2, fast);
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}
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt36x_find_mode(ap, adev->dma_mode);
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mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
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mode &= ~0xC0000000; /* Leave config bits alone */
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reg &= 0xC0000000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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static struct scsi_host_template hpt36x_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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/*
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* Configuration for HPT366/68
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*/
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static struct ata_port_operations hpt366_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = hpt366_set_piomode,
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.set_dmamode = hpt366_set_dmamode,
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.mode_filter = hpt366_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = hpt36x_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = hpt36x_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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/**
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* hpt36x_init_chipset - common chip setup
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* @dev: PCI device
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*
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* Perform the chip setup work that must be done at both init and
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* resume time
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*/
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static void hpt36x_init_chipset(struct pci_dev *dev)
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{
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u8 drive_fast;
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
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pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
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pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
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pci_read_config_byte(dev, 0x51, &drive_fast);
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if (drive_fast & 0x80)
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pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
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}
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/**
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* hpt36x_init_one - Initialise an HPT366/368
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* @dev: PCI device
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* @id: Entry in match table
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*
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* Initialise an HPT36x device. There are some interesting complications
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* here. Firstly the chip may report 366 and be one of several variants.
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* Secondly all the timings depend on the clock for the chip which we must
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* detect and look up
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*
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* This is the known chip mappings. It may be missing a couple of later
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* releases.
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*
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* Chip version PCI Rev Notes
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* HPT366 4 (HPT366) 0 UDMA66
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* HPT366 4 (HPT366) 1 UDMA66
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* HPT368 4 (HPT366) 2 UDMA66
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* HPT37x/30x 4 (HPT366) 3+ Other driver
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*
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*/
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static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static struct ata_port_info info_hpt366 = {
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.sht = &hpt36x_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = 0x1f,
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.port_ops = &hpt366_port_ops
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};
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struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
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u32 class_rev;
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u32 reg1;
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
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class_rev &= 0xFF;
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/* May be a later chip in disguise. Check */
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/* Newer chips are not in the HPT36x driver. Ignore them */
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if (class_rev > 2)
|
|
return -ENODEV;
|
|
|
|
hpt36x_init_chipset(dev);
|
|
|
|
pci_read_config_dword(dev, 0x40, ®1);
|
|
|
|
/* PCI clocking determines the ATA timing values to use */
|
|
/* info_hpt366 is safe against re-entry so we can scribble on it */
|
|
switch((reg1 & 0x700) >> 8) {
|
|
case 5:
|
|
info_hpt366.private_data = &hpt366_40;
|
|
break;
|
|
case 9:
|
|
info_hpt366.private_data = &hpt366_25;
|
|
break;
|
|
default:
|
|
info_hpt366.private_data = &hpt366_33;
|
|
break;
|
|
}
|
|
/* Now kick off ATA set up */
|
|
return ata_pci_init_one(dev, port_info, 2);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int hpt36x_reinit_one(struct pci_dev *dev)
|
|
{
|
|
hpt36x_init_chipset(dev);
|
|
return ata_pci_device_resume(dev);
|
|
}
|
|
#endif
|
|
|
|
static const struct pci_device_id hpt36x[] = {
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
|
|
{ },
|
|
};
|
|
|
|
static struct pci_driver hpt36x_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = hpt36x,
|
|
.probe = hpt36x_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
#ifdef CONFIG_PM
|
|
.suspend = ata_pci_device_suspend,
|
|
.resume = hpt36x_reinit_one,
|
|
#endif
|
|
};
|
|
|
|
static int __init hpt36x_init(void)
|
|
{
|
|
return pci_register_driver(&hpt36x_pci_driver);
|
|
}
|
|
|
|
static void __exit hpt36x_exit(void)
|
|
{
|
|
pci_unregister_driver(&hpt36x_pci_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, hpt36x);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(hpt36x_init);
|
|
module_exit(hpt36x_exit);
|