960cedb4e3
An earlier patch from Jens Osterkamp attempted to fix GDB watchpoints by enabling the DABRX register at boot time. Unfortunately, this did not work on SMP setups, where secondary CPUs were still using the power-on DABRX value. This introduces the same change for secondary CPUs on cell as well. Reported-by: Ulrich Weigand <Ulrich.Weigand@de.ibm.com> Tested-by: Ulrich Weigand <Ulrich.Weigand@de.ibm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org> |
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| .. | ||
| spufs | ||
| axon_msi.c | ||
| beat_htab.c | ||
| beat_hvCall.S | ||
| beat_interrupt.c | ||
| beat_interrupt.h | ||
| beat_iommu.c | ||
| beat_smp.c | ||
| beat_spu_priv1.c | ||
| beat_syscall.h | ||
| beat_udbg.c | ||
| beat_wrapper.h | ||
| beat.c | ||
| beat.h | ||
| cbe_cpufreq_pervasive.c | ||
| cbe_cpufreq_pmi.c | ||
| cbe_cpufreq.c | ||
| cbe_cpufreq.h | ||
| cbe_powerbutton.c | ||
| cbe_regs.c | ||
| cbe_thermal.c | ||
| celleb_pci.c | ||
| celleb_pci.h | ||
| celleb_scc_epci.c | ||
| celleb_scc_pciex.c | ||
| celleb_scc_sio.c | ||
| celleb_scc_uhc.c | ||
| celleb_scc.h | ||
| celleb_setup.c | ||
| cpufreq_spudemand.c | ||
| interrupt.c | ||
| interrupt.h | ||
| io-workarounds.c | ||
| io-workarounds.h | ||
| iommu.c | ||
| Kconfig | ||
| Makefile | ||
| pervasive.c | ||
| pervasive.h | ||
| pmu.c | ||
| ras.c | ||
| ras.h | ||
| setup.c | ||
| smp.c | ||
| spider-pci.c | ||
| spider-pic.c | ||
| spu_base.c | ||
| spu_callbacks.c | ||
| spu_fault.c | ||
| spu_manage.c | ||
| spu_notify.c | ||
| spu_priv1_mmio.c | ||
| spu_priv1_mmio.h | ||
| spu_syscalls.c | ||