43bc61d86f
This plugs in some register alignment helpers for the shared flushers, allowing them to also be used on SH-5. The main rationale here is that in the SH-5 case we have a variable ABI, where the pointer size may not equal the register width. This register extension is taken care of by the SH-5 code already today, and is otherwise unused on the SH-4 code. This combines the two and allows us to kill off the SH-5 implementation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
129 lines
3.1 KiB
C
129 lines
3.1 KiB
C
#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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/*
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* Write back the dirty D-caches, but not invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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void __weak __flush_wback_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* Write back the dirty D-caches and invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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void __weak __flush_purge_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* No write back please
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*/
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void __weak __flush_invalidate_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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