20b09c2992
This version contains following main changes - Switch to new layout to support more types of ASIC. - SSP TMF supported and related Error Handing enhanced. - Support flash feature with delay 2*HZ when PHY changed. - Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2 88SE64xx chips but any different register description. - Support SPI flash for HBA-related configuration info. - Other patch enhanced from kernel side such as increasing PHY type [jejb: fold back in DMA_BIT_MASK changes] Signed-off-by: Ying Chu <jasonchu@marvell.com> Signed-off-by: Andy Yan <ayan@marvell.com> Signed-off-by: Ke Wei <kewei@marvell.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
152 lines
4.8 KiB
C
152 lines
4.8 KiB
C
/*
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* Marvell 88SE64xx hardware specific head file
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*
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* Copyright 2007 Red Hat, Inc.
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* Copyright 2008 Marvell. <kewei@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef _MVS64XX_REG_H_
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#define _MVS64XX_REG_H_
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#include <linux/types.h>
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#define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
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/* enhanced mode registers (BAR4) */
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x08, /* global irq status */
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MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
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MVS_PHY_CTL = 0x40, /* SOC PHY Control */
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MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
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MVS_GBL_PORT_TYPE = 0xa0, /* port type */
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MVS_CTL = 0x100, /* SAS/SATA port configuration */
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MVS_PCS = 0x104, /* SAS/SATA port control/status */
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MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
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MVS_CMD_LIST_HI = 0x10C,
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MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
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MVS_RX_FIS_HI = 0x114,
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MVS_TX_CFG = 0x120, /* TX configuration */
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MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
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MVS_TX_HI = 0x128,
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MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
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MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
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MVS_RX_CFG = 0x134, /* RX configuration */
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MVS_RX_LO = 0x138, /* RX (completion) ring addr */
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MVS_RX_HI = 0x13C,
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MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
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MVS_INT_COAL = 0x148, /* Int coalescing config */
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MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
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MVS_INT_STAT = 0x150, /* Central int status */
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MVS_INT_MASK = 0x154, /* Central int enable */
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MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
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MVS_INT_MASK_SRS_0 = 0x15C,
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/* ports 1-3 follow after this */
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MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
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MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
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/* ports 5-7 follow after this */
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MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */
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MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */
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/* ports 1-3 follow after this */
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MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
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/* ports 5-7 follow after this */
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MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
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MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
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MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
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/* ports 1-3 follow after this */
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MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
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MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
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/* ports 5-7 follow after this */
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MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */
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MVS_P4_CFG_DATA = 0x234, /* Port4 config data */
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/* ports 1-3 follow after this */
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MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
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MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
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/* ports 5-7 follow after this */
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MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */
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MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */
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};
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enum pci_cfg_registers {
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PCR_PHY_CTL = 0x40,
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PCR_PHY_CTL2 = 0x90,
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PCR_DEV_CTRL = 0xE8,
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PCR_LINK_STAT = 0xF2,
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};
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/* SAS/SATA Vendor Specific Port Registers */
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enum sas_sata_vsp_regs {
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VSR_PHY_STAT = 0x00, /* Phy Status */
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VSR_PHY_MODE1 = 0x01, /* phy tx */
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VSR_PHY_MODE2 = 0x02, /* tx scc */
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VSR_PHY_MODE3 = 0x03, /* pll */
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VSR_PHY_MODE4 = 0x04, /* VCO */
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VSR_PHY_MODE5 = 0x05, /* Rx */
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VSR_PHY_MODE6 = 0x06, /* CDR */
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VSR_PHY_MODE7 = 0x07, /* Impedance */
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VSR_PHY_MODE8 = 0x08, /* Voltage */
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VSR_PHY_MODE9 = 0x09, /* Test */
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VSR_PHY_MODE10 = 0x0A, /* Power */
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VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
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VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
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VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
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};
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enum chip_register_bits {
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PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
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PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
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PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
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PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
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(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
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};
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#define MAX_SG_ENTRY 64
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struct mvs_prd {
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__le64 addr; /* 64-bit buffer address */
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__le32 reserved;
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__le32 len; /* 16-bit length */
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};
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#define SPI_CTRL_REG 0xc0
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#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
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#define SPI_CTRL_SPIRDY (1U<<22)
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#define SPI_CTRL_SPISTART (1U<<20)
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#define SPI_CMD_REG 0xc4
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#define SPI_DATA_REG 0xc8
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#define SPI_CTRL_REG_64XX 0x10
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#define SPI_CMD_REG_64XX 0x14
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#define SPI_DATA_REG_64XX 0x18
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#endif
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