422 lines
14 KiB
C
422 lines
14 KiB
C
/*
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* arch/arm/include/asm/pgtable.h
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*
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* Copyright (C) 1995-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_PGTABLE_H
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#define _ASMARM_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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#include <asm/proc-fns.h>
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#ifndef CONFIG_MMU
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#include "pgtable-nommu.h"
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#else
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#include <asm/memory.h>
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#include <mach/vmalloc.h>
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#include <asm/pgtable-hwdef.h>
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/*
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* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*
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* Note that platforms may override VMALLOC_START, but they must provide
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* VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
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* which may not overlap IO space.
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*/
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#ifndef VMALLOC_START
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#define VMALLOC_OFFSET (8*1024*1024)
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#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
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#endif
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/*
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* Hardware-wise, we have a two level page table structure, where the first
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* level has 4096 entries, and the second level has 256 entries. Each entry
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* is one 32-bit word. Most of the bits in the second level entry are used
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* by hardware, and there aren't any "accessed" and "dirty" bits.
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*
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* Linux on the other hand has a three level page table structure, which can
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* be wrapped to fit a two level page table structure easily - using the PGD
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* and PTE only. However, Linux also expects one "PTE" table per page, and
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* at least a "dirty" bit.
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*
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* Therefore, we tweak the implementation slightly - we tell Linux that we
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* have 2048 entries in the first level, each of which is 8 bytes (iow, two
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* hardware pointers to the second level.) The second level contains two
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* hardware PTE tables arranged contiguously, followed by Linux versions
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* which contain the state information Linux needs. We, therefore, end up
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* with 512 entries in the "PTE" level.
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*
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* This leads to the page tables having the following layout:
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*
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* pgd pte
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* | |
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* +--------+ +0
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* | |-----> +------------+ +0
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* +- - - - + +4 | h/w pt 0 |
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* | |-----> +------------+ +1024
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* +--------+ +8 | h/w pt 1 |
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* | | +------------+ +2048
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* +- - - - + | Linux pt 0 |
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* | | +------------+ +3072
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* +--------+ | Linux pt 1 |
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* | | +------------+ +4096
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*
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* See L_PTE_xxx below for definitions of bits in the "Linux pt", and
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* PTE_xxx for definitions of bits appearing in the "h/w pt".
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*
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* PMD_xxx definitions refer to bits in the first level page table.
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*
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* The "dirty" bit is emulated by only granting hardware write permission
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* iff the page is marked "writable" and "dirty" in the Linux PTE. This
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* means that a write to a clean page will cause a permission fault, and
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* the Linux MM layer will mark the page dirty via handle_pte_fault().
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* For the hardware to notice the permission change, the TLB entry must
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* be flushed, and ptep_set_access_flags() does that for us.
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*
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* The "accessed" or "young" bit is emulated by a similar method; we only
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* allow accesses to the page if the "young" bit is set. Accesses to the
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* page will cause a fault, and handle_pte_fault() will set the young bit
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* for us as long as the page is marked present in the corresponding Linux
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* PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
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* up to date.
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*
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* However, when the "young" bit is cleared, we deny access to the page
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* by clearing the hardware PTE. Currently Linux does not flush the TLB
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* for us in this case, which means the TLB will retain the transation
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* until either the TLB entry is evicted under pressure, or a context
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* switch which changes the user space mapping occurs.
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*/
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#define PTRS_PER_PTE 512
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PGD 2048
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/*
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* PMD_SHIFT determines the size of the area a second-level page table can map
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* PGDIR_SHIFT determines what a third-level page table entry can map
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*/
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#define PMD_SHIFT 21
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#define PGDIR_SHIFT 21
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#define LIBRARY_TEXT_START 0x0c000000
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#ifndef __ASSEMBLY__
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extern void __pte_error(const char *file, int line, unsigned long val);
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extern void __pmd_error(const char *file, int line, unsigned long val);
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extern void __pgd_error(const char *file, int line, unsigned long val);
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#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
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#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
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#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
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#endif /* !__ASSEMBLY__ */
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* This is the lowest virtual address we can permit any user space
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* mapping to be mapped at. This is particularly important for
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* non-high vector CPUs.
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*/
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#define FIRST_USER_ADDRESS PAGE_SIZE
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#define FIRST_USER_PGD_NR 1
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#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 20
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#define SECTION_SIZE (1UL << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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/*
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* ARMv6 supersection address mask and size definitions.
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*/
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#define SUPERSECTION_SHIFT 24
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#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
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#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
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/*
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* "Linux" PTE definitions.
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*
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* We keep two sets of PTEs - the hardware and the linux version.
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* This allows greater flexibility in the way we map the Linux bits
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* onto the hardware tables, and allows us to have YOUNG and DIRTY
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* bits.
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*
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* The PTE table pointer refers to the hardware entries; the "Linux"
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* entries are stored 1024 bytes below.
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*/
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#define L_PTE_PRESENT (1 << 0)
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#define L_PTE_FILE (1 << 1) /* only when !PRESENT */
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#define L_PTE_YOUNG (1 << 1)
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#define L_PTE_BUFFERABLE (1 << 2) /* obsolete, matches PTE */
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#define L_PTE_CACHEABLE (1 << 3) /* obsolete, matches PTE */
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#define L_PTE_DIRTY (1 << 6)
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#define L_PTE_WRITE (1 << 7)
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#define L_PTE_USER (1 << 8)
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#define L_PTE_EXEC (1 << 9)
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#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
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/*
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* These are the memory types, defined to be compatible with
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* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
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*/
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#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
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#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
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#define L_PTE_MT_WRITETHROUGH (0x02 << 2) /* 0010 */
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#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
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#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
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#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
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#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
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#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
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#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
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#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
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#define L_PTE_MT_MASK (0x0f << 2)
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#ifndef __ASSEMBLY__
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/*
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* The pgprot_* and protection_map entries will be fixed up in runtime
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* to include the cachable and bufferable bits based on memory policy,
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* as well as any architecture dependent bits like global/ASID and SMP
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* shared mapping bits.
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*/
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#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
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extern pgprot_t pgprot_user;
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extern pgprot_t pgprot_kernel;
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#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
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#define PAGE_NONE pgprot_user
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#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE)
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#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
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#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER)
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#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
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#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER)
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#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
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#define PAGE_KERNEL pgprot_kernel
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#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_kernel, L_PTE_EXEC)
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#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
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#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE)
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#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
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#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
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#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
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#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
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#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
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#endif /* __ASSEMBLY__ */
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/*
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* The table below defines the page protection levels that we insert into our
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* Linux page table version. These get translated into the best that the
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* architecture can perform. Note that on most ARM hardware:
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* 1) We cannot do execute protection
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* 2) If we could do execute protection, then read is implied
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* 3) write implies read permissions
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*/
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#define __P000 __PAGE_NONE
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#define __P001 __PAGE_READONLY
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#define __P010 __PAGE_COPY
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#define __P011 __PAGE_COPY
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#define __P100 __PAGE_READONLY_EXEC
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#define __P101 __PAGE_READONLY_EXEC
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#define __P110 __PAGE_COPY_EXEC
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#define __P111 __PAGE_COPY_EXEC
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#define __S000 __PAGE_NONE
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#define __S001 __PAGE_READONLY
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#define __S010 __PAGE_SHARED
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#define __S011 __PAGE_SHARED
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#define __S100 __PAGE_READONLY_EXEC
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#define __S101 __PAGE_READONLY_EXEC
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#define __S110 __PAGE_SHARED_EXEC
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#define __S111 __PAGE_SHARED_EXEC
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#ifndef __ASSEMBLY__
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern struct page *empty_zero_page;
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#define ZERO_PAGE(vaddr) (empty_zero_page)
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define pte_none(pte) (!pte_val(pte))
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#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
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#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
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#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
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#define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
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#define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
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#define set_pte_at(mm,addr,ptep,pteval) do { \
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set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
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} while (0)
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
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#define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
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#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
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#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
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#define pte_special(pte) (0)
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/*
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* The following only works if pte_present() is not true.
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*/
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#define pte_file(pte) (pte_val(pte) & L_PTE_FILE)
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#define pte_to_pgoff(x) (pte_val(x) >> 2)
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#define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE)
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#define PTE_FILE_MAX_BITS 30
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#define PTE_BIT_FUNC(fn,op) \
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static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
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PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
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PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE);
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PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY);
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PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY);
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PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
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PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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/*
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* Mark the prot value as uncacheable and unbufferable.
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*/
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#define pgprot_noncached(prot) \
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__pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_UNCACHED)
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#define pgprot_writecombine(prot) \
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__pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_BUFFERABLE)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_present(pmd) (pmd_val(pmd))
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#define pmd_bad(pmd) (pmd_val(pmd) & 2)
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#define copy_pmd(pmdpd,pmdps) \
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do { \
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pmdpd[0] = pmdps[0]; \
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pmdpd[1] = pmdps[1]; \
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flush_pmd_entry(pmdpd); \
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} while (0)
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#define pmd_clear(pmdp) \
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do { \
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pmdp[0] = __pmd(0); \
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pmdp[1] = __pmd(0); \
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clean_pmd_entry(pmdp); \
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} while (0)
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static inline pte_t *pmd_page_vaddr(pmd_t pmd)
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{
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unsigned long ptr;
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ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
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ptr += PTRS_PER_PTE * sizeof(void *);
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return __va(ptr);
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}
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#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
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/*
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* The "pgd_xxx()" functions here are trivial for a folded two-level
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* setup: the pgd is never bad, and a pmd always exists (as it's folded
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* into the pgd entry)
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*/
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#define pgd_none(pgd) (0)
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#define pgd_bad(pgd) (0)
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#define pgd_present(pgd) (1)
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#define pgd_clear(pgdp) do { } while (0)
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#define set_pgd(pgd,pgdp) do { } while (0)
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/* to find an entry in a page-table-directory */
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#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
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#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(dir, addr) ((pmd_t *)(dir))
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/* Find an entry in the third-level page table.. */
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#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
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pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
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return pte;
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}
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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/* Encode and decode a swap entry.
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*
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* We support up to 32GB of swap on 4k machines
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*/
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#define __swp_type(x) (((x).val >> 2) & 0x7f)
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#define __swp_offset(x) ((x).val >> 9)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
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/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
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/* FIXME: this is not correct */
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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/*
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* We provide our own arch_get_unmapped_area to cope with VIPT caches.
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*/
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#define HAVE_ARCH_UNMAPPED_AREA
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/*
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* remap a physical page `pfn' of size `size' with page protection `prot'
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* into virtual address `from'
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*/
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#define io_remap_pfn_range(vma,from,pfn,size,prot) \
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remap_pfn_range(vma, from, pfn, size, prot)
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#define pgtable_cache_init() do { } while (0)
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#endif /* !__ASSEMBLY__ */
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#endif /* CONFIG_MMU */
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#endif /* _ASMARM_PGTABLE_H */
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