04ea1cc8ab
When GENERIC_HARDIRQS_NO_DEPRECATED is enabled, a number of struct irq_desc members stop being directly accessible, and need to be accessed via the irq_data struct instead -- this patch fixes up the plat-samsung sites that still access those members directly. Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* arch/arm/plat-samsung/irq-vic-timer.c
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* originally part of arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/regs-timer.h>
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static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
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{
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generic_handle_irq((int)desc->irq_data.handler_data);
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_mask(struct irq_data *data)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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reg &= 0x1f; /* mask out pending interrupts */
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reg &= ~mask;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_unmask(struct irq_data *data)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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reg &= 0x1f; /* mask out pending interrupts */
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reg |= mask;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_ack(struct irq_data *data)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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u32 mask = (u32)data->chip_data;
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reg &= 0x1f;
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reg |= mask << 5;
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static struct irq_chip s3c_irq_timer = {
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.name = "s3c-timer",
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.irq_mask = s3c_irq_timer_mask,
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.irq_unmask = s3c_irq_timer_unmask,
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.irq_ack = s3c_irq_timer_ack,
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};
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/**
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* s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
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* @parent_irq: The parent IRQ on the VIC for the timer.
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* @timer_irq: The IRQ to be used for the timer.
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*
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* Register the necessary IRQ chaining and support for the timer IRQs
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* chained of the VIC.
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*/
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void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
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unsigned int timer_irq)
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{
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struct irq_desc *desc = irq_to_desc(parent_irq);
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set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
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set_irq_chip(timer_irq, &s3c_irq_timer);
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set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
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set_irq_handler(timer_irq, handle_level_irq);
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set_irq_flags(timer_irq, IRQF_VALID);
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desc->irq_data.handler_data = (void *)timer_irq;
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}
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