8c34974ab0
All of the clocks that are marked with DELAYED_APP are changed as part of the virt_prcm_set OPP virtual clock. On 24xx, these clocks all need to be changed as part of a group to keep the clock tree functional - hence the need for the VALID_CONFIG bit, which is not present on later OMAPs. These clocks should not be rate-changed independently. So prevent these clocks from being changed independently by dropping their .round_rate and .set_rate function pointers. It then turns out that the DELAYED_APP clock flag is no longer useful, so drop it and the associated code and renumber the clock flags. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
414 lines
11 KiB
C
414 lines
11 KiB
C
/*
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* clkt_clksel.c - OMAP2/3/4 clksel clock functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX At some point these clksel clocks should be split into
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* "divider" clocks and "mux" clocks to better match the hardware.
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*
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* XXX Currently these clocks are only used in the OMAP2/3/4 code, but
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* many of the OMAP1 clocks should be convertible to use this
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* mechanism.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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/* Private functions */
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/**
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* _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
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* @clk: OMAP struct clk ptr to inspect
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* @src_clk: OMAP struct clk ptr of the parent clk to search for
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*
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* Scan the struct clksel array associated with the clock to find
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* the element associated with the supplied parent clock address.
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* Returns a pointer to the struct clksel on success or NULL on error.
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*/
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static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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{
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const struct clksel *clks;
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if (!clk->clksel)
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return NULL;
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for (clks = clk->clksel; clks->parent; clks++) {
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if (clks->parent == src_clk)
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break; /* Found the requested parent */
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}
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if (!clks->parent) {
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printk(KERN_ERR "clock: Could not find parent clock %s in "
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"clksel array of clock %s\n", src_clk->name,
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clk->name);
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return NULL;
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}
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return clks;
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}
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/*
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* Converts encoded control register address into a full address
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* On error, the return value (parent_div) will be 0.
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*/
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static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
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u32 *field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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clks = _omap2_get_clksel_by_parent(clk, src_clk);
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
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break; /* Found the default rate for this platform */
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}
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if (!clkr->div) {
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printk(KERN_ERR "clock: Could not find default rate for "
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"clock %s parent %s\n", clk->name,
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src_clk->parent->name);
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return 0;
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}
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/* Should never happen. Add a clksel mask to the struct clk. */
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WARN_ON(clk->clksel_mask == 0);
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*field_val = clkr->val;
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return clkr->div;
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}
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/* Public functions */
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/**
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* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
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* @clk: OMAP clock struct ptr to use
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*
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* Given a pointer to a source-selectable struct clk, read the hardware
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* register and determine what its parent is currently set to. Update the
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* clk->parent field with the appropriate clk ptr.
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*/
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void omap2_init_clksel_parent(struct clk *clk)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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if (!clk->clksel)
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return;
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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for (clks = clk->clksel; clks->parent && !found; clks++) {
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for (clkr = clks->rates; clkr->div && !found; clkr++) {
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if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
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if (clk->parent != clks->parent) {
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pr_debug("clock: inited %s parent "
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"to %s (was %s)\n",
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clk->name, clks->parent->name,
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((clk->parent) ?
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clk->parent->name : "NULL"));
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clk_reparent(clk, clks->parent);
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};
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found = 1;
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}
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}
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}
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if (!found)
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printk(KERN_ERR "clock: init parent: could not find "
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"regval %0x for clock %s\n", r, clk->name);
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return;
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}
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/*
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* Used for clocks that are part of CLKSEL_xyz governed clocks.
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* REVISIT: Maybe change to use clk->enable() functions like on omap1?
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*/
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unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
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u32 div = 0;
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pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
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div = omap2_clksel_get_divisor(clk);
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if (div == 0)
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return clk->rate;
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rate = clk->parent->rate / div;
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pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
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return rate;
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}
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/**
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* omap2_clksel_round_rate_div - find divisor for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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* @new_div: ptr to where we should store the divisor
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*
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* Finds 'best' divider value in an array based on the source and target
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* rates. The divider array must be sorted with smallest divider first.
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* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
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* they are only settable as part of virtual_prcm set.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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u32 *new_div)
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{
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unsigned long test_rate;
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 last_div = 0;
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pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk->name, target_rate);
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*new_div = 1;
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clks = _omap2_get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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/* Sanity check */
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if (clkr->div <= last_div)
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pr_err("clock: clksel_rate table not sorted "
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"for clock %s", clk->name);
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last_div = clkr->div;
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test_rate = clk->parent->rate / clkr->div;
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if (test_rate <= target_rate)
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break; /* found it */
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}
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if (!clkr->div) {
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pr_err("clock: Could not find divisor for target "
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"rate %ld for clock %s parent %s\n", target_rate,
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clk->name, clk->parent->name);
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return ~0;
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}
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*new_div = clkr->div;
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pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
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(clk->parent->rate / clkr->div));
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return clk->parent->rate / clkr->div;
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}
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/**
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* omap2_clksel_round_rate - find rounded rate for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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*
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* Compatibility wrapper for OMAP clock framework
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* Finds best target rate based on the source clock and possible dividers.
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* rates. The divider array must be sorted with smallest divider first.
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* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
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* they are only settable as part of virtual_prcm set.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
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{
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u32 new_div;
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return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
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}
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/* Given a clock and a rate apply a clock specific rounding function */
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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if (clk->flags & RATE_FIXED)
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printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
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"on fixed-rate clock %s\n", clk->name);
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return clk->rate;
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}
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/**
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* omap2_clksel_to_divisor() - turn clksel field value into integer divider
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* @clk: OMAP struct clk to use
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* @field_val: register field value to find
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*
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* Given a struct clk of a rate-selectable clksel clock, and a register field
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* value to search for, find the corresponding clock divisor. The register
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* field value should be pre-masked and shifted down so the LSB is at bit 0
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* before calling. Returns 0 on error
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*/
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u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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clks = _omap2_get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
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break;
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}
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if (!clkr->div) {
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printk(KERN_ERR "clock: Could not find fieldval %d for "
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"clock %s parent %s\n", field_val, clk->name,
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clk->parent->name);
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return 0;
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}
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return clkr->div;
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}
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/**
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* omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
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* @clk: OMAP struct clk to use
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* @div: integer divisor to search for
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*
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* Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
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* find the corresponding register field value. The return register value is
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* the value before left-shifting. Returns ~0 on error
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*/
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u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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/* should never happen */
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WARN_ON(div == 0);
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clks = _omap2_get_clksel_by_parent(clk, clk->parent);
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if ((clkr->flags & cpu_mask) && (clkr->div == div))
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break;
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}
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if (!clkr->div) {
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printk(KERN_ERR "clock: Could not find divisor %d for "
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"clock %s parent %s\n", div, clk->name,
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clk->parent->name);
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return ~0;
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}
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return clkr->val;
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}
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/**
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* omap2_clksel_get_divisor - get current divider applied to parent clock.
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* @clk: OMAP struct clk to use.
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*
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* Returns the integer divisor upon success or 0 on error.
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*/
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u32 omap2_clksel_get_divisor(struct clk *clk)
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{
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u32 v;
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if (!clk->clksel_mask)
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return 0;
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v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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v >>= __ffs(clk->clksel_mask);
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return omap2_clksel_to_divisor(clk, v);
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}
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 v, field_val, validrate, new_div = 0;
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if (!clk->clksel_mask)
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return -EINVAL;
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validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
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if (validrate != rate)
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return -EINVAL;
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field_val = omap2_divisor_to_clksel(clk, new_div);
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if (field_val == ~0)
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return -EINVAL;
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v = __raw_readl(clk->clksel_reg);
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v &= ~clk->clksel_mask;
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v |= field_val << __ffs(clk->clksel_mask);
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__raw_writel(v, clk->clksel_reg);
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v = __raw_readl(clk->clksel_reg); /* OCP barrier */
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clk->rate = clk->parent->rate / new_div;
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return 0;
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}
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int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
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{
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u32 field_val, v, parent_div;
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if (!clk->clksel)
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return -EINVAL;
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parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
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if (!parent_div)
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return -EINVAL;
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/* Set new source value (previous dividers if any in effect) */
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v = __raw_readl(clk->clksel_reg);
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v &= ~clk->clksel_mask;
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v |= field_val << __ffs(clk->clksel_mask);
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__raw_writel(v, clk->clksel_reg);
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v = __raw_readl(clk->clksel_reg); /* OCP barrier */
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clk_reparent(clk, new_parent);
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/* CLKSEL clocks follow their parents' rates, divided by a divisor */
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clk->rate = new_parent->rate;
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if (parent_div > 0)
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clk->rate /= parent_div;
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pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
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clk->name, clk->parent->name, clk->rate);
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return 0;
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}
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