8e313211f7
Core changes: None. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put(). -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmacNaMACgkQQRCzN7AZ XXM2zBAApbYm8ftQ0Og6AKEapMUWWQl8eo0TMG4E81vqx9oAs0qDjFvKyHioy/Gm ZKwfmRPFqg/rxWP4eFOCE/dQwL7gELPOIiJJOlV+qF9dUcQo/cdSPze//mt06iTl xRnKL8/r+LlFU2qBcfqzdrqeCV52TZUhRrYlau+9CxGkFTF7KVNQossInMPC91gY aClovH5CDn1pl8SOziGOpPVqv9UJR0KkEDeoroWQ6IcBx3OutAan77KySpJFThcJ ZHN7cNYPgLItmJz7ERXtWumVRM4sRZ0jwQeUE9A+tMuTyhplguKHDeZjRxojoGkM HcYA7WUUrMPNzc9163+7A9qEhMzR6HINFBtysRWuQolofYq44w50/v6DL5xvdOoe 1adJzxH+JiBRWQ4fTq4Gc2QEICY59kmHamOrGLGCqeIldMRC+fQCHF+4mnqMSbru eXuvdXjzPes1KflmaHmb6s2AxJjYLmIdcfsElMAy7uz9hghzPhYUeq0157Fa3Igp M7dK1Wh9lGjudLvEXz6ZW/OV57eOo+Xc7yISVi/OnD+qiMejnzNoEcy83zSa/7sh O/BlbuHOwVv+Gysgs0Fphu9GjZuPuzjT8NyKlzouFgrUE38LojY/Dz1SF1FYJL+9 9t6TbnJnpmPwVMT3p63BmSj5f3iTUXqGd0IPqCZltTc1rPl7X/w= =79pj -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ...
548 lines
16 KiB
C
548 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Pinmux and GPIO driver for tps6594 PMIC
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*
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* Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
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*/
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#include <linux/gpio/driver.h>
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#include <linux/gpio/regmap.h>
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#include <linux/module.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mfd/tps6594.h>
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#define TPS6594_PINCTRL_GPIO_FUNCTION 0
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#define TPS6594_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION 1
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#define TPS6594_PINCTRL_TRIG_WDOG_FUNCTION 1
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#define TPS6594_PINCTRL_CLK32KOUT_FUNCTION 1
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#define TPS6594_PINCTRL_SCLK_SPMI_FUNCTION 1
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#define TPS6594_PINCTRL_SDATA_SPMI_FUNCTION 1
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#define TPS6594_PINCTRL_NERR_MCU_FUNCTION 1
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#define TPS6594_PINCTRL_PDOG_FUNCTION 1
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#define TPS6594_PINCTRL_SYNCCLKIN_FUNCTION 1
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#define TPS6594_PINCTRL_NRSTOUT_SOC_FUNCTION 2
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#define TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION 2
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#define TPS6594_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION 2
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#define TPS6594_PINCTRL_NERR_SOC_FUNCTION 2
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#define TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION 3
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#define TPS6594_PINCTRL_NSLEEP1_FUNCTION 4
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#define TPS6594_PINCTRL_NSLEEP2_FUNCTION 5
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#define TPS6594_PINCTRL_WKUP1_FUNCTION 6
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#define TPS6594_PINCTRL_WKUP2_FUNCTION 7
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/* Special muxval for recalcitrant pins */
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#define TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8 2
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#define TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8 3
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#define TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9 3
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/* TPS65224 pin muxval */
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#define TPS65224_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION 1
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#define TPS65224_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION 1
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#define TPS65224_PINCTRL_VMON1_FUNCTION 1
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#define TPS65224_PINCTRL_VMON2_FUNCTION 1
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#define TPS65224_PINCTRL_WKUP_FUNCTION 1
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#define TPS65224_PINCTRL_NSLEEP2_FUNCTION 2
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#define TPS65224_PINCTRL_NSLEEP1_FUNCTION 2
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#define TPS65224_PINCTRL_SYNCCLKIN_FUNCTION 2
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#define TPS65224_PINCTRL_NERR_MCU_FUNCTION 2
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#define TPS65224_PINCTRL_NINT_FUNCTION 3
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#define TPS65224_PINCTRL_TRIG_WDOG_FUNCTION 3
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#define TPS65224_PINCTRL_PB_FUNCTION 3
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#define TPS65224_PINCTRL_ADC_IN_FUNCTION 3
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/* TPS65224 Special muxval for recalcitrant pins */
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#define TPS65224_PINCTRL_NSLEEP2_FUNCTION_GPIO5 1
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#define TPS65224_PINCTRL_WKUP_FUNCTION_GPIO5 4
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#define TPS65224_PINCTRL_SYNCCLKIN_FUNCTION_GPIO5 3
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#define TPS6594_OFFSET_GPIO_SEL 5
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#define TPS65224_NGPIO_PER_REG 6
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#define TPS6594_NGPIO_PER_REG 8
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#define FUNCTION(dev_name, fname, v) \
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{ \
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.pinfunction = PINCTRL_PINFUNCTION(#fname, \
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dev_name##_##fname##_func_group_names, \
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ARRAY_SIZE(dev_name##_##fname##_func_group_names)),\
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.muxval = v, \
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}
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static const struct pinctrl_pin_desc tps6594_pins[] = {
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PINCTRL_PIN(0, "GPIO0"), PINCTRL_PIN(1, "GPIO1"),
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PINCTRL_PIN(2, "GPIO2"), PINCTRL_PIN(3, "GPIO3"),
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PINCTRL_PIN(4, "GPIO4"), PINCTRL_PIN(5, "GPIO5"),
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PINCTRL_PIN(6, "GPIO6"), PINCTRL_PIN(7, "GPIO7"),
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PINCTRL_PIN(8, "GPIO8"), PINCTRL_PIN(9, "GPIO9"),
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PINCTRL_PIN(10, "GPIO10"),
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};
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static const char *const tps6594_gpio_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
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};
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static const char *const tps6594_nsleep1_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
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};
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static const char *const tps6594_nsleep2_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
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};
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static const char *const tps6594_wkup1_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
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};
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static const char *const tps6594_wkup2_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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"GPIO6", "GPIO7", "GPIO8", "GPIO9", "GPIO10",
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};
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static const char *const tps6594_scl_i2c2_cs_spi_func_group_names[] = {
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"GPIO0",
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"GPIO1",
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};
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static const char *const tps6594_nrstout_soc_func_group_names[] = {
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"GPIO0",
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"GPIO10",
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};
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static const char *const tps6594_trig_wdog_func_group_names[] = {
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"GPIO1",
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"GPIO10",
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};
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static const char *const tps6594_sda_i2c2_sdo_spi_func_group_names[] = {
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"GPIO1",
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};
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static const char *const tps6594_clk32kout_func_group_names[] = {
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"GPIO2",
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"GPIO3",
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"GPIO7",
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};
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static const char *const tps6594_nerr_soc_func_group_names[] = {
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"GPIO2",
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};
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static const char *const tps6594_sclk_spmi_func_group_names[] = {
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"GPIO4",
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};
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static const char *const tps6594_sdata_spmi_func_group_names[] = {
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"GPIO5",
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};
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static const char *const tps6594_nerr_mcu_func_group_names[] = {
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"GPIO6",
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};
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static const char *const tps6594_syncclkout_func_group_names[] = {
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"GPIO7",
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"GPIO9",
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};
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static const char *const tps6594_disable_wdog_func_group_names[] = {
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"GPIO7",
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"GPIO8",
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};
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static const char *const tps6594_pdog_func_group_names[] = {
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"GPIO8",
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};
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static const char *const tps6594_syncclkin_func_group_names[] = {
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"GPIO9",
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};
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static const struct pinctrl_pin_desc tps65224_pins[] = {
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PINCTRL_PIN(0, "GPIO0"), PINCTRL_PIN(1, "GPIO1"),
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PINCTRL_PIN(2, "GPIO2"), PINCTRL_PIN(3, "GPIO3"),
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PINCTRL_PIN(4, "GPIO4"), PINCTRL_PIN(5, "GPIO5"),
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};
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static const char *const tps65224_gpio_func_group_names[] = {
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"GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4", "GPIO5",
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};
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static const char *const tps65224_sda_i2c2_sdo_spi_func_group_names[] = {
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"GPIO0",
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};
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static const char *const tps65224_nsleep2_func_group_names[] = {
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"GPIO0", "GPIO5",
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};
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static const char *const tps65224_nint_func_group_names[] = {
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"GPIO0",
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};
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static const char *const tps65224_scl_i2c2_cs_spi_func_group_names[] = {
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"GPIO1",
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};
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static const char *const tps65224_nsleep1_func_group_names[] = {
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"GPIO1", "GPIO2", "GPIO3",
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};
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static const char *const tps65224_trig_wdog_func_group_names[] = {
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"GPIO1",
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};
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static const char *const tps65224_vmon1_func_group_names[] = {
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"GPIO2",
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};
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static const char *const tps65224_pb_func_group_names[] = {
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"GPIO2",
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};
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static const char *const tps65224_vmon2_func_group_names[] = {
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"GPIO3",
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};
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static const char *const tps65224_adc_in_func_group_names[] = {
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"GPIO3", "GPIO4",
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};
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static const char *const tps65224_wkup_func_group_names[] = {
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"GPIO4", "GPIO5",
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};
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static const char *const tps65224_syncclkin_func_group_names[] = {
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"GPIO4", "GPIO5",
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};
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static const char *const tps65224_nerr_mcu_func_group_names[] = {
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"GPIO5",
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};
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struct tps6594_pinctrl_function {
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struct pinfunction pinfunction;
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u8 muxval;
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};
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struct muxval_remap {
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unsigned int group;
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u8 muxval;
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u8 remap;
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};
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static struct muxval_remap tps65224_muxval_remap[] = {
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{5, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS65224_PINCTRL_WKUP_FUNCTION_GPIO5},
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{5, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION_GPIO5},
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{5, TPS65224_PINCTRL_NSLEEP2_FUNCTION, TPS65224_PINCTRL_NSLEEP2_FUNCTION_GPIO5},
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};
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static struct muxval_remap tps6594_muxval_remap[] = {
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{8, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8},
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{8, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8},
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{9, TPS6594_PINCTRL_CLK32KOUT_FUNCTION, TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9},
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};
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static const struct tps6594_pinctrl_function pinctrl_functions[] = {
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FUNCTION(tps6594, gpio, TPS6594_PINCTRL_GPIO_FUNCTION),
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FUNCTION(tps6594, nsleep1, TPS6594_PINCTRL_NSLEEP1_FUNCTION),
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FUNCTION(tps6594, nsleep2, TPS6594_PINCTRL_NSLEEP2_FUNCTION),
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FUNCTION(tps6594, wkup1, TPS6594_PINCTRL_WKUP1_FUNCTION),
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FUNCTION(tps6594, wkup2, TPS6594_PINCTRL_WKUP2_FUNCTION),
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FUNCTION(tps6594, scl_i2c2_cs_spi, TPS6594_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION),
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FUNCTION(tps6594, nrstout_soc, TPS6594_PINCTRL_NRSTOUT_SOC_FUNCTION),
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FUNCTION(tps6594, trig_wdog, TPS6594_PINCTRL_TRIG_WDOG_FUNCTION),
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FUNCTION(tps6594, sda_i2c2_sdo_spi, TPS6594_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION),
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FUNCTION(tps6594, clk32kout, TPS6594_PINCTRL_CLK32KOUT_FUNCTION),
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FUNCTION(tps6594, nerr_soc, TPS6594_PINCTRL_NERR_SOC_FUNCTION),
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FUNCTION(tps6594, sclk_spmi, TPS6594_PINCTRL_SCLK_SPMI_FUNCTION),
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FUNCTION(tps6594, sdata_spmi, TPS6594_PINCTRL_SDATA_SPMI_FUNCTION),
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FUNCTION(tps6594, nerr_mcu, TPS6594_PINCTRL_NERR_MCU_FUNCTION),
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FUNCTION(tps6594, syncclkout, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION),
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FUNCTION(tps6594, disable_wdog, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION),
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FUNCTION(tps6594, pdog, TPS6594_PINCTRL_PDOG_FUNCTION),
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FUNCTION(tps6594, syncclkin, TPS6594_PINCTRL_SYNCCLKIN_FUNCTION),
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};
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static const struct tps6594_pinctrl_function tps65224_pinctrl_functions[] = {
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FUNCTION(tps65224, gpio, TPS6594_PINCTRL_GPIO_FUNCTION),
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FUNCTION(tps65224, sda_i2c2_sdo_spi, TPS65224_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION),
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FUNCTION(tps65224, nsleep2, TPS65224_PINCTRL_NSLEEP2_FUNCTION),
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FUNCTION(tps65224, nint, TPS65224_PINCTRL_NINT_FUNCTION),
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FUNCTION(tps65224, scl_i2c2_cs_spi, TPS65224_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION),
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FUNCTION(tps65224, nsleep1, TPS65224_PINCTRL_NSLEEP1_FUNCTION),
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FUNCTION(tps65224, trig_wdog, TPS65224_PINCTRL_TRIG_WDOG_FUNCTION),
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FUNCTION(tps65224, vmon1, TPS65224_PINCTRL_VMON1_FUNCTION),
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FUNCTION(tps65224, pb, TPS65224_PINCTRL_PB_FUNCTION),
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FUNCTION(tps65224, vmon2, TPS65224_PINCTRL_VMON2_FUNCTION),
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FUNCTION(tps65224, adc_in, TPS65224_PINCTRL_ADC_IN_FUNCTION),
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FUNCTION(tps65224, wkup, TPS65224_PINCTRL_WKUP_FUNCTION),
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FUNCTION(tps65224, syncclkin, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION),
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FUNCTION(tps65224, nerr_mcu, TPS65224_PINCTRL_NERR_MCU_FUNCTION),
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};
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struct tps6594_pinctrl {
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struct tps6594 *tps;
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struct gpio_regmap *gpio_regmap;
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struct pinctrl_dev *pctl_dev;
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const struct tps6594_pinctrl_function *funcs;
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const struct pinctrl_pin_desc *pins;
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int func_cnt;
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int num_pins;
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u8 mux_sel_mask;
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unsigned int remap_cnt;
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struct muxval_remap *remap;
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};
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static struct tps6594_pinctrl tps65224_template_pinctrl = {
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.funcs = tps65224_pinctrl_functions,
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.func_cnt = ARRAY_SIZE(tps65224_pinctrl_functions),
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.pins = tps65224_pins,
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.num_pins = ARRAY_SIZE(tps65224_pins),
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.mux_sel_mask = TPS65224_MASK_GPIO_SEL,
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.remap = tps65224_muxval_remap,
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.remap_cnt = ARRAY_SIZE(tps65224_muxval_remap),
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};
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static struct tps6594_pinctrl tps6594_template_pinctrl = {
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.funcs = pinctrl_functions,
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.func_cnt = ARRAY_SIZE(pinctrl_functions),
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.pins = tps6594_pins,
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.num_pins = ARRAY_SIZE(tps6594_pins),
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.mux_sel_mask = TPS6594_MASK_GPIO_SEL,
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.remap = tps6594_muxval_remap,
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.remap_cnt = ARRAY_SIZE(tps6594_muxval_remap),
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};
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static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio,
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unsigned int base, unsigned int offset,
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unsigned int *reg, unsigned int *mask)
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{
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unsigned int line = offset % 8;
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unsigned int stride = offset / 8;
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switch (base) {
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case TPS6594_REG_GPIOX_CONF(0):
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*reg = TPS6594_REG_GPIOX_CONF(offset);
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*mask = TPS6594_BIT_GPIO_DIR;
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return 0;
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case TPS6594_REG_GPIO_IN_1:
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case TPS6594_REG_GPIO_OUT_1:
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*reg = base + stride;
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*mask = BIT(line);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int tps6594_pmx_func_cnt(struct pinctrl_dev *pctldev)
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{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pinctrl->func_cnt;
|
|
}
|
|
|
|
static const char *tps6594_pmx_func_name(struct pinctrl_dev *pctldev,
|
|
unsigned int selector)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pinctrl->funcs[selector].pinfunction.name;
|
|
}
|
|
|
|
static int tps6594_pmx_func_groups(struct pinctrl_dev *pctldev,
|
|
unsigned int selector,
|
|
const char *const **groups,
|
|
unsigned int *num_groups)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*groups = pinctrl->funcs[selector].pinfunction.groups;
|
|
*num_groups = pinctrl->funcs[selector].pinfunction.ngroups;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tps6594_pmx_set(struct tps6594_pinctrl *pinctrl, unsigned int pin,
|
|
u8 muxval)
|
|
{
|
|
u8 mux_sel_val = muxval << TPS6594_OFFSET_GPIO_SEL;
|
|
u8 mux_sel_mask = pinctrl->mux_sel_mask;
|
|
|
|
if (pinctrl->tps->chip_id == TPS65224 && pin == 5) {
|
|
/* GPIO6 has a different mask in TPS65224*/
|
|
mux_sel_mask = TPS65224_MASK_GPIO_SEL_GPIO6;
|
|
}
|
|
|
|
return regmap_update_bits(pinctrl->tps->regmap,
|
|
TPS6594_REG_GPIOX_CONF(pin),
|
|
mux_sel_mask, mux_sel_val);
|
|
}
|
|
|
|
static int tps6594_pmx_set_mux(struct pinctrl_dev *pctldev,
|
|
unsigned int function, unsigned int group)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
u8 muxval = pinctrl->funcs[function].muxval;
|
|
unsigned int remap_cnt = pinctrl->remap_cnt;
|
|
struct muxval_remap *remap = pinctrl->remap;
|
|
|
|
for (unsigned int i = 0; i < remap_cnt; i++) {
|
|
if (group == remap[i].group && muxval == remap[i].muxval) {
|
|
muxval = remap[i].remap;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return tps6594_pmx_set(pinctrl, group, muxval);
|
|
}
|
|
|
|
static int tps6594_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int offset, bool input)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
u8 muxval = pinctrl->funcs[TPS6594_PINCTRL_GPIO_FUNCTION].muxval;
|
|
|
|
return tps6594_pmx_set(pinctrl, offset, muxval);
|
|
}
|
|
|
|
static const struct pinmux_ops tps6594_pmx_ops = {
|
|
.get_functions_count = tps6594_pmx_func_cnt,
|
|
.get_function_name = tps6594_pmx_func_name,
|
|
.get_function_groups = tps6594_pmx_func_groups,
|
|
.set_mux = tps6594_pmx_set_mux,
|
|
.gpio_set_direction = tps6594_pmx_gpio_set_direction,
|
|
.strict = true,
|
|
};
|
|
|
|
static int tps6594_groups_cnt(struct pinctrl_dev *pctldev)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pinctrl->num_pins;
|
|
}
|
|
|
|
static int tps6594_group_pins(struct pinctrl_dev *pctldev,
|
|
unsigned int selector, const unsigned int **pins,
|
|
unsigned int *num_pins)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*pins = &pinctrl->pins[selector].number;
|
|
*num_pins = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const char *tps6594_group_name(struct pinctrl_dev *pctldev,
|
|
unsigned int selector)
|
|
{
|
|
struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pinctrl->pins[selector].name;
|
|
}
|
|
|
|
static const struct pinctrl_ops tps6594_pctrl_ops = {
|
|
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
|
|
.dt_free_map = pinconf_generic_dt_free_map,
|
|
.get_groups_count = tps6594_groups_cnt,
|
|
.get_group_name = tps6594_group_name,
|
|
.get_group_pins = tps6594_group_pins,
|
|
};
|
|
|
|
static int tps6594_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
|
|
struct device *dev = &pdev->dev;
|
|
struct tps6594_pinctrl *pinctrl;
|
|
struct pinctrl_desc *pctrl_desc;
|
|
struct gpio_regmap_config config = {};
|
|
|
|
pctrl_desc = devm_kzalloc(dev, sizeof(*pctrl_desc), GFP_KERNEL);
|
|
if (!pctrl_desc)
|
|
return -ENOMEM;
|
|
|
|
pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
|
|
if (!pinctrl)
|
|
return -ENOMEM;
|
|
|
|
switch (tps->chip_id) {
|
|
case TPS65224:
|
|
pctrl_desc->pins = tps65224_pins;
|
|
pctrl_desc->npins = ARRAY_SIZE(tps65224_pins);
|
|
|
|
*pinctrl = tps65224_template_pinctrl;
|
|
|
|
config.ngpio = ARRAY_SIZE(tps65224_gpio_func_group_names);
|
|
config.ngpio_per_reg = TPS65224_NGPIO_PER_REG;
|
|
break;
|
|
case TPS6593:
|
|
case TPS6594:
|
|
case LP8764:
|
|
pctrl_desc->pins = tps6594_pins;
|
|
pctrl_desc->npins = ARRAY_SIZE(tps6594_pins);
|
|
|
|
*pinctrl = tps6594_template_pinctrl;
|
|
|
|
config.ngpio = ARRAY_SIZE(tps6594_gpio_func_group_names);
|
|
config.ngpio_per_reg = TPS6594_NGPIO_PER_REG;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
pinctrl->tps = tps;
|
|
|
|
pctrl_desc->name = dev_name(dev);
|
|
pctrl_desc->owner = THIS_MODULE;
|
|
pctrl_desc->pctlops = &tps6594_pctrl_ops;
|
|
pctrl_desc->pmxops = &tps6594_pmx_ops;
|
|
|
|
config.parent = tps->dev;
|
|
config.regmap = tps->regmap;
|
|
config.reg_dat_base = TPS6594_REG_GPIO_IN_1;
|
|
config.reg_set_base = TPS6594_REG_GPIO_OUT_1;
|
|
config.reg_dir_out_base = TPS6594_REG_GPIOX_CONF(0);
|
|
config.reg_mask_xlate = tps6594_gpio_regmap_xlate;
|
|
|
|
pinctrl->pctl_dev = devm_pinctrl_register(dev, pctrl_desc, pinctrl);
|
|
if (IS_ERR(pinctrl->pctl_dev))
|
|
return dev_err_probe(dev, PTR_ERR(pinctrl->pctl_dev),
|
|
"Couldn't register pinctrl driver\n");
|
|
|
|
pinctrl->gpio_regmap = devm_gpio_regmap_register(dev, &config);
|
|
if (IS_ERR(pinctrl->gpio_regmap))
|
|
return dev_err_probe(dev, PTR_ERR(pinctrl->gpio_regmap),
|
|
"Couldn't register gpio_regmap driver\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id tps6594_pinctrl_id_table[] = {
|
|
{ "tps6594-pinctrl", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, tps6594_pinctrl_id_table);
|
|
|
|
static struct platform_driver tps6594_pinctrl_driver = {
|
|
.probe = tps6594_pinctrl_probe,
|
|
.driver = {
|
|
.name = "tps6594-pinctrl",
|
|
},
|
|
.id_table = tps6594_pinctrl_id_table,
|
|
};
|
|
module_platform_driver(tps6594_pinctrl_driver);
|
|
|
|
MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");
|
|
MODULE_AUTHOR("Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>");
|
|
MODULE_DESCRIPTION("TPS6594 pinctrl and GPIO driver");
|
|
MODULE_LICENSE("GPL");
|