93641ecbaa
The cavium IP can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions in both the octeon and thunder bus driver. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
124 lines
2.8 KiB
C
124 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2009-2016 Cavium, Inc.
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*/
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enum cavium_mdiobus_mode {
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UNINIT = 0,
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C22,
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C45
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};
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#define SMI_CMD 0x0
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#define SMI_WR_DAT 0x8
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#define SMI_RD_DAT 0x10
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#define SMI_CLK 0x18
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#define SMI_EN 0x20
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#ifdef __BIG_ENDIAN_BITFIELD
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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field; \
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more
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#else
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#define OCT_MDIO_BITFIELD_FIELD(field, more) \
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more \
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field;
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#endif
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union cvmx_smix_clk {
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u64 u64;
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struct cvmx_smix_clk_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
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OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
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OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
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OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
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OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
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OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
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OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
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;))))))))))
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} s;
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};
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union cvmx_smix_cmd {
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u64 u64;
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struct cvmx_smix_cmd_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
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OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
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OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
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;))))))
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} s;
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};
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union cvmx_smix_en {
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u64 u64;
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struct cvmx_smix_en_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
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OCT_MDIO_BITFIELD_FIELD(u64 en:1,
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;))
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} s;
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};
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union cvmx_smix_rd_dat {
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u64 u64;
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struct cvmx_smix_rd_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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union cvmx_smix_wr_dat {
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u64 u64;
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struct cvmx_smix_wr_dat_s {
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OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
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OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
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OCT_MDIO_BITFIELD_FIELD(u64 val:1,
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OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
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;))))
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} s;
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};
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struct cavium_mdiobus {
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struct mii_bus *mii_bus;
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void __iomem *register_base;
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enum cavium_mdiobus_mode mode;
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};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
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{
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cvmx_write_csr((u64 __force)addr, val);
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}
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static inline u64 oct_mdio_readq(void __iomem *addr)
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{
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return cvmx_read_csr((u64 __force)addr);
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}
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#else
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#include <linux/io-64-nonatomic-lo-hi.h>
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#define oct_mdio_writeq(val, addr) writeq(val, addr)
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#define oct_mdio_readq(addr) readq(addr)
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#endif
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int cavium_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int regnum);
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int cavium_mdiobus_write_c22(struct mii_bus *bus, int phy_id, int regnum,
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u16 val);
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int cavium_mdiobus_read_c45(struct mii_bus *bus, int phy_id, int devad,
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int regnum);
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int cavium_mdiobus_write_c45(struct mii_bus *bus, int phy_id, int devad,
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int regnum, u16 val);
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